AM29F004B AMD [Advanced Micro Devices], AM29F004B Datasheet - Page 19

• Manufacturer Part Number: AM29F004B
• Description: 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

WRITE OPERATION STATUS
The device provides several bits to determine the status of a
write operation: DQ2, DQ3, DQ5, DQ6, and DQ7.
page 19
of these bits. DQ7 and DQ6 each offer a method for deter-
mining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data# Polling is
valid after the rising edge of the final WE# pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on DQ7 the complement of the datum programmed to DQ7.
This DQ7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is com-
plete, the device outputs the datum programmed to DQ7. The
system must provide the program address to read valid status
information on DQ7. If a program address falls within a pro-
t e c t e d s e c t o r, D a t a # Po l l i n g o n D Q 7 i s a c t i ve fo r
approximately 2 µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data# Polling pro-
duces a “0” on DQ7. When the Embedded Erase algorithm is
complete, or if the device enters the Erase Suspend mode,
Data# Polling produces a “1” on DQ7. This is analogous to
the complement/true datum output described for the
Embedded Program algorithm: the erase function changes
all the bits in a sector to “1”; prior to this, the device outputs
the “complement,” or “0.” The system must provide an
address within any of the sectors selected for erasure to read
valid status information on DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7 is
active for approximately 100 µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are protected.
When the system detects DQ7 changes from the comple-
ment to true data, it can read valid data at DQ7–DQ0 on the
following read cycles. This is because DQ7 may change
asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low. The Data# Polling Timings (During Embedded
Algorithms) figure in the
section illustrates this.
Table 6 on page 19
DQ7.
algorithm.
8/5/05
Figure 5, on page 17
and the following subsections describe the functions
shows the outputs for Data# Polling on
AC Characteristics on page 24
shows the Data# Polling
A D V A N C E
Table 6 on
Am29F004B
I N F O R M A T I O N
Notes:
1. VA = Valid address for programming. During a sector erase
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may
operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any
non-protected sector address.
change simultaneously with DQ5.
No
Figure 5. Data# Polling Algorithm
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
Yes
Yes
PASS
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