EVAL-AD5620EB AD [Analog Devices], EVAL-AD5620EB Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD5620EB
• Description: Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
• Manufacturer: AD [Analog Devices]

AD5620/AD5640/AD5660
INPUT SHIFT REGISTER
AD5620/AD5640
The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 40 and Figure 41). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16th falling edge of SCLK.
AD5660
The input shift register is 24 bits wide for the AD5660 (see
Figure 42). The first six bits are don’t care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
SYNC
SCLK
DB23 (MSB)
DIN
X
X
SYNC HIGH BEFORE 16
X
MSB
INVALID WRITE SEQUENCE:
DB15 (MSB)
DB15 (MSB)
PD1
PD1
X
X
PD0
PD0
TH
/24
X
D13
D11
TH
FALLING EDGE
PD1
LSB
D12
D10
PD0
D11
D9
D15
Figure 40. AD5620 Input Register Contents
Figure 41. AD5640 Input Register Contents
Figure 42. AD5660 Input Register Contents
D10
D8
Figure 43. SYNC Interrupt Facility
D14
D7
D9
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D13
DATA BITS
D6
D8
D12
DATA BITS
D5
D7
D10
SYNC INTERRUPT
In a normal write sequence for the AD5660, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs—see Figure 43.
Similarly, in a normal write sequence for the AD5620/AD5640,
the SYNC line is kept low for at least 16 falling edges of SCLK,
and the DAC is updated on the 16th falling edge. However, if
SYNC is brought high before the 16th falling edge, this acts as
an interrupt to the write sequence.
D4
D6
D9
VALID WRITE SEQUENCE, OUTPUT UPDATES
D3
D5
DATA BITS
D8
ON THE 16
MSB
D2
D4
D7
D1
D3
TH
D6
/24
TH
D0
D2
D5
FALLING EDGE
D1
X
D4
DB0 (LSB)
DB0 (LSB)
LSB
D0
D3
X
D2
D1
DB0 (LSB)
D0