EVAL-AD5533EB AD [Analog Devices], EVAL-AD5533EB Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD5533EB
• Description: 32-Channel Precision Infinite Sample-and-Hold
• Manufacturer: AD [Analog Devices]

AD5533B
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter
t
t
t
t
t
t
NOTES
1
2
Specifications subject to change without notice.
SERIAL INTERFACE
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
See Parallel Interface Timing Diagram.
Guaranteed by design and characterization, not production tested.
See Serial Interface Timing Diagrams.
Guaranteed by design and characterization, not production tested.
These numbers are measured with the load circuit of Figure 2.
SYNC should be taken low while SCLK is low for readback.
1
2
3
4
5
6
CLKIN
1
2
3
4
5
6
7
8
9
10
11
3
3
4
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (ISHA Mode Only)
WR
CS
1, 2
1, 2
Limit at T
(B Version)
0
0
50
50
20
7
Limit at T
(B Version)
20
20
20
15
50
10
5
5
20
60
400
7
MIN
MIN
, T
, T
MAX
MAX
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
–4–
Conditions/Comments
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
D
D
SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback
SCLK Rising Edge to D
SCLK Falling Edge to D
10th SCLK Falling Edge to SYNC Falling Edge for Readback
SCLK Falling Edge to SYNC Falling Edge Setup Time for
Readback
IN
IN
Conditions/Comments
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
Setup Time
Hold Time
Figure 2. Load Circuit for D
OUTPUT
PIN
TO
OUT
OUT
Valid
High Impedance
50pF
C
L
200 A
200 A
OUT
Timing Specifications
I
I
OH
OL
1.6V
REV. A