EVAL-AD5533EB AD [Analog Devices], EVAL-AD5533EB Datasheet - Page 13

• Manufacturer Part Number: EVAL-AD5533EB
• Description: 32-Channel Precision Infinite Sample-and-Hold
• Manufacturer: AD [Analog Devices]

REV. A
DB13–DB0 Bit
These are used in both readback modes to read a 14-bit word
from the addressed DAC register.
The serial interface is designed to allow easy interfacing to most
microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI™,
SPI™, DSP56000, TMS320, and ADSP-21xx, without the
need for any glue logic. When interfacing to the 8051, the
SCLK must be inverted. The Microprocessor/Microcontroller
Interface section explains how to interface to some popular
DSPs and microcontrollers.
Figures 3 and 4 show the timing diagram for a serial read and
write to the AD5533B. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC resets a counter that counts the number of serial
clocks to ensure the correct number of bits are shifted in and out
of the serial shift registers. Any further edges on SYNC are ignored
until the correct number of bits are shifted in or out. Once the
correct number of bits have been shifted in or out, the SCLK is
ignored. In order for another serial transfer to take place, the
counter must be reset by the falling edge of SYNC. In readback,
the first rising SCLK edge after the falling edge of SYNC causes
D
onto the D
The D
edge of the 14th SCLK. Data on the D
first SCLK falling edge after the falling edge of the SYNC signal
and on subsequent SCLK falling edges. The serial interface will
not shift data in or out until it receives the falling edge of the
SYNC signal.
*SPI and QSPI are trademarks of Motorola, Inc.
OUT
to leave its high impedance state and data is clocked out
OUT
pin goes back into a high impedance state on the falling
OUT
line and also on subsequent SCLK rising edges.
MSB
MSB
1
1
MODE BITS
MODE BITS
MSB
MODE BIT 1
b. Input Serial Interface (Acquire and Readback Mode)
1
0
IN
0
line is latched in on the
MODE BITS
a. 10-Bit Input Serial Write Word (ISHA Mode)
WRITTEN TO PART
WRITTEN TO PART
c. Input Serial Interface (Readback Mode)
SERIAL WORD
SERIAL WORD
CAL
MODE BIT 2
0
Figure 8. Serial Interface Formats
10-BIT
10-BIT
0
OFFSET SEL
OFFSET SEL
CAL
–13–
TEST BIT
TEST BIT
0
OFFSET SEL
Parallel Interface
The SER/PAR bit is tied low to enable the parallel interface and
disable the serial interface. The parallel interface is controlled
by nine pins as follows:
MICROPROCESSOR INTERFACING
AD5533B to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5533B without the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5533B on the falling edge of its SCLK. In
0
CS
Active low package select pin. This pin is shared with the
SYNC function for the serial interface.
WR
Active low write pin. The values on the address pins are
latched on a rising edge of WR.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These
are used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel
is addressed and the address on A4–A0 is ignored.
Cal
Same functionality as the Cal bit in the serial interface. When
this pin is high, all 32 channels acquire V
A4–A0
A4–A0
LSB
LSB
TEST BIT
0
NEXT FALLING EDGE OF SYNC
NEXT FALLING EDGE OF SYNC
(DB13 = MSB OF DAC WORD)
(DB13 = MSB OF DAC WORD)
READ FROM PART AFTER
READ FROM PART AFTER
MSB
MSB
A4–A0
14-BIT DATA
14-BIT DATA
DB1 3 –DB0
DB1 3 –DB0
LSB
LSB
LSB
IN
AD5533B
simultaneously.