EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

EVAL-AD1896EB
TYPICAL PERFORMANCE
Typical performance of the AD1896 for 44.1 kHz:48 kHz (asynchronous) sample rate is listed below.
1. DNR, No Filter
2. DNR, A-Weighted
3. THD+N, No Filter
4. Frequency Response
EXTERNAL 192 kHz CLOCK GENERATOR CIRCUIT
An external circuit can be used to generate the 192 kHz clock
signals (SCLK, LRCLK) using on-board 128
tor (U15) running at 24.576 MHz. Please refer to Figure 4 for
the schematic and instructions on how to connect the exter-
nal circuit to the AD1896EB. In general, external SCLK and
LRCLK can be used for converting the audio input data to 192 kHz
rate by connecting SCLK to SCLK_O (DDO_SCLK_O,
HDR5 on the AD1896EB) and LRCLK to LRCLK_O
(DDO_LRCLK_O, HDR5 on the AD1896EB). On-board SPDIF
transmitter CS8404 (U6) does not support sample rates above
96 kHz.
DEFAULT SETUP
INPUT DATA:
DIRECT DIGITAL INPUT HEADER
HDR3 (DDI)
Sample Rate (kHz)
44.100
48.000
96.000
Table IX. MCLK_I Frequencies for Common Sample Rates in Master Mode
SET EXTERNALLY
–139 dBFS, 20 Hz to 20 kHz (–60 dBFS)
–142 dBFS, 20 Hz to 20 kHz (–60 dBFS)
–120 dBFS, 20 Hz to 20 kHz (0 dBFS)
± 0.015 dB, 20 Hz to 20 kHz (0 dBFS)
f
S_IN
LRCLK
SDATA
SCLK
JUMPER JP4
44.1kHz
1
f
S_OUT
2 3
f
S
clock oscilla-
SCLK_I
LRCLK_I
SDATA_I
MCLK_I
33.868MHz CRYSTAL
256
11.289600
12.288000
24.576000
AD1896
U13
LRCLK_O
SDATA_O
MCLK_O
SCLK_O
f
S
CLOCK DIVIDER
MCLK_I Frequency (MHz)
ATTACHMENTS
Appendix A
1. External 192 kHz Clock Generator Circuit
2. AD1896 Evaluation Board Block Diagram, Schematics, and
3. Bill of Materials
4. PLD Code
FURTHER INFORMATION
Ordering Information
Order number is EVAL-AD1896EB
For Application Questions or Technical Support
Contact Analog Devices’ Central Applications Department at
1-781-937-1428 for assistance.
128
256f
Layout Plots
f
S
S
512
22.579200
24.576000
OUTPUT DATA:
DIRECT DIGITAL OUTPUT HEADER
HDR5 (DDO)
MCLK_I
LRCLK_I
SDATA_I
LRCLK
SDATA
SDATA_I
LRCLK_I
SCLK_I
MCLK_I
SCLK_I
SCLK
AD1852 DAC
CS8404 DIT
256
128
f
S
f
f
U12
U6
S
S
768
33.868800
LEFT OUT
RIGHT OUT
SPDIF OUTPUT
f
S