EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

DIGITAL AUDIO INPUT SIGNALS
Input serial port of the AD1896 can be driven in various ways
using this evaluation board.
1. RCA phone jack (J1) or TOSLINK (U4) optical connector
2. Alternatively, an external data header (HDR3) can be used
can be used to input the AES/EBU or SPDIF signal to the
SPDIF receiver CS8414 (U1). SPDIF receiver generated
SCLK_I, LRCLK_I, and SDATA_I signals drive the input
serial port of the AD1896. SPDIF input is supported only
when the AD1896 serial input port is in SLAVE mode (Switch
S4 position 3 to 7) and supports all input serial data formats
except RJ-24 bit and RJ-20 bit (Switch S3 positions 2, 3). The
SPDIF receiver limits input sample rates to 96 kHz.
to directly source all three signals SCLK_I, LRCLK_I, and
SDATA_I from an external source. Unlike SPDIF receiver,
S4 Switch Position
7
6
5
4
3
2
1
0
In MASTER MODE operation, maximum sample rate for Master Port is limited to 96 kHz.
Pin
1
3
5
7
2, 4, 6, 8, 10
JP4 CRYSTAL OSC./EXTERNAL CLK
S3 (8-POSITION SWITCH)
DDI-HDR3, SPDIF-J1,
HDR1 (TDM_IN)
5 V (O)
TDM_I (I)
SCLK_O (I/O)
LRCLK_O (I/O)
GND
TOSLINK-U4
Table I. Pinout Table for 10-Pin Header Connectors
S8
S6
S5
S7
Table II. Input and Output Serial Port Modes
MMODE_[2:0]
0
0
0
0
1
1
1
1
2
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
1
0
0
1
1
0
0
1
1
GRPDLYS
MUTE_IN
MCLK_O
LRCLK_I
SDATA_I
BYPASS
MCLK_I
VDD_IO
SCLK_I
RESET
DGND
HDR2 (TDM_OUT)
5 V (O)
SDATA_O (O)
SCLK_O (I/O)
LRCLK_O (I/O)
GND
0
0
1
0
1
0
1
0
1
10
11
12
13
14
1
2
3
4
5
6
7
8
9
AD1896
SCLK_I and LRCLK_I signals of the input serial port are
bidirectional signals. Logic levels on pins MMODE_ [2:0]
control the direction of these signals. When the input serial port
is in master mode, these signals are generated by the AD1896;
whereas, in the slave mode these signals are provided by an
external source. MMODE_[2:0] pins are set by the 8-position
Switch S4. Tables II and III show the master/slave clock mode
corresponding to each switch position.
Input data format, such as, I
levels on SMODE_IN_[2:0] pins as shown in Table IV. Set the
8-position Switch S3 on the evaluation board for the proper
input data format.
Master/Slave Modes
Both Serial Ports are in Slave Mode
Matched Phase Mode
*Input Serial Port is Master with 256
input sample rate up to 192 kHz is possible (input port in
slave mode) and set by an external source. All input serial
data formats and master/slave clock modes are supported.
Output Serial Port is Master with 768
Output Serial Port is Master with 512
Output Serial Port is Master with 256
Input Serial Port is Master with 768
Input Serial Port is Master with 512
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MMODE_2
MMODE_1
MMODE_0
SCLK_O
LRCLK_O
SDATA_O
VDD_CORE
DGND
TDM_IN
SMODE_OUT_0
SMODE_OUT_1
WLNGTH_OUT_0
WLNGTH_OUT_1
MUTE_OUT
HDR3 (DDI)
5 V (O)
SDATA_I (I)
LRCLK_I (I/O)
SCLK_I (I/O)
GND
S4 (8-POSITION SWITCH)
DDO-HDR5, SPDIF-J2,
TDM_OUT-HDR2
TDM IN HEADER HDR1
JP1 (4-POSITION JUMPER)
2
S, LJ, or RJ is set by the logic
EVAL-AD1896EB
HDR5 (DDO)
5 V (O)
SDATA_O (O)
SCLK_O (I/O)
LRCLK_O (I/O)
GND
f
f
f
S
S_IN
S_IN
_IN
f
f
f
S_OUT
S_OUT
S_OUT