SH3000UM SEMTECH [Semtech Corporation], SH3000UM Datasheet - Page 20

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SH3000UM

Manufacturer Part Number
SH3000UM
Description
Manufacturer
SEMTECH [Semtech Corporation]
Datasheet
Interrupt and Serial Interface
A single line is used to convey bi-directional information
between the SH3003 and the processor, and as the inter-
rupt line to the processor.
The polarity of the interrupt signal is programmable. The
SH3003 and the host microcontroller communicate using
a single wire, bi-directional asynchronous serial interface.
The bit rate is automatically determined by the SH3003.
At the fastest possible rate, a read or write access of a
single byte from the register bank takes 5μs.
The SH3003 contains thirty-six addressable registers
located at 0x00–0x1F. Some of these registers are ac-
cessed through a page operation. Pin 14, IO/Int, is the
serial communications interface and interrupt output pin.
This pin is internally weakly pulled to the opposite of the
programmed interrupt polarity. For example, if interrupt is
programmed to be active low, this pin is weakly pulled to
V
As shown in Figure 7, the SH3003 and the host commu-
nicate with serial data streams. The host always initiates
communication. A data stream consists of the following
(in this order):
Plus, for write streams only:
The 3-bit start fi eld (1,0,1 or 0,1,0, depending on interrupt
polarity) uses the middle bit to determine the bit period of
the serial data stream.
©2006 Semtech Corp.
POWER MANAGEMENT
Application Information
DD
• 3-bit start fi eld
• 3-bit read/write code
• 5-bit address fi eld
• 1 guard bit
• 8-bit data fi eld
• 2 parity bits
• 1 guard bit
• 2 acknowledge (ACK) bits
when inactive.
(continued)
Not authorized for release outside of Semtech
20
The 3-bit read/write code consists of 1,1,0 for a read, or
0,1,1 for a write. This protects against early glitches that
might otherwise put the interface into an invalid read or
write access mode.
The 5-bit address fi eld contains the address of the regis-
ter. A single guard bit gives the interface a safe period in
which to change data direction. The value of a guard bit
does not matter. The 8-bit data fi eld is written to (read
from) the register.
Two parity bits: The fi rst parity bit is high when there are
an odd number of bits in the read/write, address and data
fi elds; the second parity bit is the inverse of the fi rst.
For write streams only, a guard bit is appended to the
stream (to allow safe turnaround), and then two acknowl-
edge bits, which are a direct copy of the parity bits, are
driven back to the host to indicate a successful write ac-
cess.
Two guard bits are appended to the end of the access
stream (read or write). The host can not start the next ac-
cess before receiving these bits.
The interface is self-timed based on the duration of the
start bit fi eld, and communication can take place when-
ever CLKout is active, either at 32.768kHz or at a higher
frequency. If the host microcontroller is running synchro-
nously to the CLKout generated by the SH3003 (which
should generally be the case), then a minimum of four
CLKout cycles per bit are required to maintain communi-
cation integrity. If the host’s serial interface is asynchro-
nous to CLKout, then a minimum of 52 cycles per bit are
necessary. A maximum of 1024 CLKout cycles per bit fi eld
is supported.
Table 3 displays the minimum and maximum bit periods
for the serial communications for CLKout frequencies of
16 MHz, 8MHz, and 2MHz.
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SH3003
- DRAFT

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