GS8161Z18 GSI [GSI Technology], GS8161Z18 Datasheet - Page 28

• Manufacturer Part Number: GS8161Z18
• Description: 18Mb Pipelined and Flow Through Synchronous NBT SRAM
• Manufacturer: GSI [GSI Technology]

JTAG TAP Instruction Set Summary
Rev: 2.15 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
Instruction
SAMPLE-Z
PRELOAD
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
SAMPLE/
IDCODE
BYPASS
EXTEST
RFU
RFU
GSI
Code
000
001
010
011
100
101
110
111
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
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GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Description
© 1998, GSI Technology
Notes
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1
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