VRS51C1100-40-L ETC1 [List of Unclassifed Manufacturers], VRS51C1100-40-L Datasheet - Page 20

• Manufacturer Part Number: VRS51C1100-40-L
• Description: Versa 8051 MCU with 128KB of IAP/ISP Flash
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Mode 0
A schematic representation of this mode of operation is
presented in the figure below. In Mode 0, the timer
operates as a 13-bit counter made up of 5 LSBs of the
TLx register and the 8 upper bits of the THx register.
When an overflow causes the value of the register to
rollover to 0, the TFx interrupt signal goes to 1. The
count value is validated as soon as TRx goes to 1 and
the GATE bit is 0, or when INTx is 1.
F
Mode 1
Mode 1 is almost identical to Mode 0, the difference
being that in Mode 1, the counter/timer uses the full
16-bits of the timer.
Mode 2
In this Mode, the register of the timer is configured as
an 8-bit automatically re-loadable counter/timer. In
Mode 2, the lower byte TLx is used as the counter. In
the event of a counter overflow, the TFx flag is set to 1
and the value contained in THx, which is preset by
software, is reloaded into the TLx counter. The value of
THx remains unchanged.
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IGURE
TR1/TR0
GATE1 /
T1/T0 pin
GATE0
INT1 /
INT0 pin
VRS51C1100
Fosc
11: T
IMER
/C
OUNTER
÷12
1 M
ODE
0
1
C/T1 / C/T0 =0
C/T1 / CT0 =1
0: 13-B
IT
Control
C
OUNTER
CLK
0
0
TH1 / TH0
TL1 / TL0
Mode 0
Mode 1
TF1 /
TF0
4
7
7
INT
Mode 3
In Mode 3, Timer 1 is blocked as if its control bit, TR1,
was set to 0. In this mode, Timer 0’s registers, TL0 and
TH0, are configured as two separate 8-bit counters.
The TL0 counter uses Timer 0’s control bits (C/T,
GATE, TR0, INT0, TF0), and the TH0 counter is held
in timer mode (counting machine cycles) and gains
control over TR1 and TF1 from Timer 1. At this point,
TH0 controls the Timer 1 interrupt.
F
F
INT0 PIN
IGURE
T1 / T0 Pin
INT1 / INT0 pin
IGURE
TR1 / TR0
GATE1 / GATE0
GATE
TR0
Fosc
T0PIN
Fosc
12: T
13: T
IMER
IMER
/C
/C
OUNTER
OUNTER
÷12
÷12
1 M
0 M
ODE
ODE
0
1
0
1
C/T =0
C/T =1
2: 8-
3
C/T1 / C/T0 = 1
C/T1 / C/T0 = 1
BIT
A
Control
Control
Control
UTOMATIC
TR1
R
CLK
CLK
ELOAD
0
0
page 20 of 50
0
0
TF1
TF0
TH1 / TH0
TF1 / TF0
TL1 / TL0
TH0
TL0
INTERRUPT
INTERRUPT
7
7
7
7
INT
Reload