VRS51C1100-40-L ETC1 [List of Unclassifed Manufacturers], VRS51C1100-40-L Datasheet - Page 15

• Manufacturer Part Number: VRS51C1100-40-L
• Description: Versa 8051 MCU with 128KB of IAP/ISP Flash
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

The bit addressable P0 register, located at address
80h, controls the P0 individual pin directions when
used as I/Os (see the following table).
T
Port 2
Port P2 is similar to ports 1 and 3, the difference being
that P2 is used to drive the A8-A15 lines of the address
bus when the EA line of VRS51C1100 is held low at
reset time or when a MOVX instruction is executed.
Like the P0, P1 and P3 registers, the P2 register is bit
addressable.
T
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ABLE
ABLE
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
P0.7
P2.7
VRS51C1100
7
7
17: P
18: P
ORT
ORT
Mnemonic
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P0.6
P2.6
6
6
0 R
2 R
EGISTER
EGISTER
P0.5
P2.5
5
5
(P0) - SFR 80
(P2) - SFR A0
Description
For each bit of the P0 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
Description
For each bit of the P2 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up brings the I/O to 5V.
P0.4
P2.4
4
4
H
H
P0.3
P2.3
3
3
P0.2
P2.2
2
2
P0.1
P2.1
1
1
P0.0
P2.0
0
0
Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources:
Internal Bus
When the ports are used as an address or data bus,
special function registers P0 and P2 are disconnected
from the output stage, the 8 bits of the P0 register are
forced to 1 and the contents of the P2 register remains
constant.
Port 1
The P1 register controls the direction of the Port 1 I/O
pins. Writing a 1 into the P1.x bit (see the following
table) of the P1 register configures the bit as an output,
presenting a logic 1 to the corresponding I/O pin or
enables use of the I/O pin as an input. Writing a 0
activates the output “pull-down” transistor, which will
force the corresponding I/O line to a logic low.
T
F
IGURE
Write to
Register
ABLE
Bit
7
6
5
4
3
2
1
0
P1.7
Read Register
7
o
o
19: P
Read Pin
9: P2 P
ORT
Mnemonic
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0
The outputs of the P2 register or the high byte
(A8 through A15) of the bus address for the P2
port
P1.6
6
ORT
1 R
S
EGISTER
TRUCTURE
P1.5
5
D Flip-Flop
(P2) - SFR 90
Description
For each bit of the P1 register correspond
to an I/O line:
0: Output transistor pull the line to 0V
1: The output transistor is blocked so the
pull-up bring the I/O to 5V.
Q
Q
P1.4
4
Control
H
P1.3
3
Address
P1.2
2
page 15 of 50
Vcc
X1
Pull-up
Network
P1.1
1
P1.0
IC Pin
0