GS840Z18AGT-100 GSI [GSI Technology], GS840Z18AGT-100 Datasheet

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GS840Z18AGT-100

Manufacturer Part Number
GS840Z18AGT-100
Description
4Mb Pipelined and Flow Through Synchronous NBT SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin compatible with both pipelined and flow through
• Pin-compatible with 2M, 8M and 16M devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
The GS840Z18/36AT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization
NtRAM™, NoBL™ and ZBT™ SRAMs
Through
Pipeline
3-1-1-1
2-1-1-1
4Mb Pipelined and Flow Through
Flow
Synchronous NBT SRAMs
tCycle
tCycle
t
I
t
I
KQ
DD
KQ
DD
Parameter Synopsis
335 mA
210 mA
1/24
5.5 ns
3.2 ns
9.1 ns
–180
8 ns
310 mA
190 mA
6.0 ns
3.5 ns
8.5 ns
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS840Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS840Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
10 ns
–166
280 mA
165 mA
6.6 ns
3.8 ns
10 ns
12 ns
–150
GS840Z18/36AT-180/166/150/100
190 mA
135 mA
4.5 ns
10 ns
12 ns
15 ns
–100
2.5 V and 3.3 V V
© 2001, GSI Technology
180 MHz–100 MHz
3.3 V V
DDQ
DD

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GS840Z18AGT-100 Summary of contents

Page 1

Pipelined and Flow Through 100-Pin TQFP Commercial Temp Industrial Temp Features • 256K x 18 and 128K x 36 configurations • User configurable Pipeline and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait read-write-read ...

Page 2

DDQ ...

Page 3

DQP DDQ ...

Page 4

TQFP Pin Descriptions Symbol Type ...

Page 5

GS840Z18/36A NBT SRAM Functional Block Diagram Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840Z18/36AT-180/166/150/100 Amps Sense Drivers Write 5/24 © 2001, GSI Technology ...

Page 6

Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in ...

Page 7

Synchronous Truth Table Operation Type Address CK CKE ADV Read Cycle, Begin Burst R Read Cycle, Continue Burst B NOP/Read, Begin Burst R Dummy Read, Continue Burst B Write Cycle, Begin Burst W Write Cycle, Continue Burst ...

Page 8

Pipelined and Flow Through Read-Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for ...

Page 9

Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.03 11/2004 Specifications cited are subject to change without notice. ...

Page 10

B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) n Clock (CK) Command Current State Current State and Next State Definition for: Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For ...

Page 11

Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address ...

Page 12

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal ...

Page 13

Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...

Page 14

V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...

Page 15

Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...

Page 16

DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For ...

Page 17

Operating Currents Parameter Test Conditions Symbol Device Selected; Operating All other inputs Current ≥V or ≤ Output open Standby ZZ ≥ V – DD Current 0.2 V Device Deselected; Deselect All other inputs Current ≥ ...

Page 18

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Clock ...

Page 19

Write A Read CKE ADV Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation ...

Page 20

Write A Write CKE ADV A0– D(A) G *Note High(False ...

Page 21

TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

Page 22

... GS840Z36AT-100I 256K x 18 GS840Z18AGT-180 256K x 18 GS840Z18AGT-166 256K x 18 GS840Z18AGT-150 256K x 18 GS840Z18AGT-100 128K x 36 GS840Z36AGT-180 128K x 36 GS840Z36AGT-166 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8Z36A-100IT. 2. ...

Page 23

... GS840Z36AGT-150 128K x 36 GS840Z36AGT-100 256K x 18 GS840Z18AGT-180I 256K x 18 GS840Z18AGT-166I 256K x 18 GS840Z18AGT-150I 256K x 18 GS840Z18AGT-100I 128K x 36 GS840Z36AGT-180I 128K x 36 GS840Z36AGT-166I 128K x 36 GS840Z36AGT-150I 128K x 36 GS840Z36AGT-100I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8Z36A-100IT. ...

Page 24

Synchronous NBT Datasheet Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New 840Z18A_r1 840Z18A_r1; 840Z18A_r1_01 840Z18A_r1_01; 840Z18A_r1_02 840Z18A_r1_02; 840Z18A_r1_03 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page ...

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