AS7C33128PFS18B-133TQC ALSC [Alliance Semiconductor Corporation], AS7C33128PFS18B-133TQC Datasheet - Page 6

• Manufacturer Part Number: AS7C33128PFS18B-133TQC
• Description: 3.3V 128K x 18 pipeline burst synchronous SRAM
• Manufacturer: ALSC [Alliance Semiconductor Corporation]

Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b;
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Write All Bytes
Write Byte a
Write Byte b
Read
Snooze mode
Read
Write
Deselected
1
2
3
4
12/10/04; v.1.4
st
nd
rd
th
Address
Address
Address
Address
Operation
Function
Interleaved burst address (LBO = 1)
A1 A0
0 0
0 1
1 0
1 1
ZZ
GWE
H
L
L
L
L
H
H
H
H
H
L
A1 A0
0 1
0 0
1 1
1 0
BWE
X
H
L
L
L
L
OE
X
H
X
X
A1 A0
L
BWE
1 0
1 1
0 0
0 1
,
BWa
Alliance Semiconductor
BWn
X
H
X
H
L
L
Din, High-Z
A1 A0
I/O Status
1 1
1 0
0 1
0 0
High-Z
High-Z
High-Z
= internal write signal.
Dout
BWb
X
H
X
H
L
L
1
2
3
4
st
nd
rd
th
Address
Address
Address
Address
®
Linear burst address (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
A1 A0
0 1
1 0
1 1
1 0
A1 A0
AS7C33128PFS18B
1 0
1 1
0 0
0 1
A1 A0
1 1
0 0
0 1
1 0
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