GS8160E18BGT-150 GSI [GSI Technology], GS8160E18BGT-150 Datasheet

GS8160E18BGT-150

Manufacturer Part Number

GS8160E18BGT-150

Description

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS8160E18BGT-150.pdf (23 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline opera-

• Dual Cycle Deselect (DCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS8160E18/32/36BT is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.03 9/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tion

Flow Through

Pipeline

3-1-1-1

2-1-1-1

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/23

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8160E18/32/36BT is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8160E18/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

-250

295

345

225

255

2.5

4.0

5.5

-200

245

285

200

220

3.0

5.0

6.5

DDQ

GS8160E18/32/36BT-250/200/150

) pins are used to decouple output noise

-150

200

225

185

205

3.8

6.7

7.5

Unit

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160E18BGT-150

GS8160E18BGT-150 Summary of contents

Page 1

TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline opera- tion • Dual Cycle Deselect (DCD) operation • 2 3.3 V +10%/–10% core power supply • 2 3.3 V ...

Page 2

DDQ ...

Page 3

DDQ ...

Page 4

DQP DDQ ...

Page 5

TQFP Pin Description Symbol Type I ...

Page 6

Page 7

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: Thereis a pull-up deviceonthe FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will ...

Page 8

Byte Write Enable inputs and/ All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “ ” and “ ...

Page 9

Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B control ...

Page 10

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...

Page 11

Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...

Page 12

V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...

Page 13

Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...

Page 14

DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For ...

Page 15

Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...

Page 16

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...

Page 17

Begin Read A Cont CK ADSP tS tH ADSC tS ADV tS tH Ao– Ba– tOE DQa–DQd Hi-Z Rev: 1.03 9/2005 Specifications cited are subject ...

Page 18

Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tH tS ADV tS tH Ao– Ba– and E3 only sampled with ADSP and ADSC ...

Page 19

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 20

TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

Page 21

... GS8160E32BT-200I 512K x 32 GS8160E32BT-150I 512K x 36 GS8160E36BT-250I 512K x 36 GS8160E36BT-200I 512K x 36 GS8160E36BT-150I GS8160E18BGT-250 GS8160E18BGT-200 GS8160E18BGT-150 512K x 32 GS8160E32BGT-250 512K x 32 GS8160E32BGT-200 512K x 32 GS8160E32BGT-150 512K x 36 GS8160E36BGT-250 512K x 36 GS8160E36BGT-200 512K x 36 GS8160E36BGT-150 GS8160E18BGT-250I ...

Page 22

... Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number GS8160E18BGT-150I 512K x 32 GS8160E32BGT-250I 512K x 32 GS8160E32BGT-200I 512K x 32 GS8160E32BGT-150I 512K x 36 GS8160E36BGT-250I 512K x 36 GS8160E36BGT-200I 512K x 36 GS8160E36BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18B-150IT. ...

Page 23

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content GS8160ExxB_r1 8160ExxB_r1; 8160ExxB_r1_01 8160ExxB_r1_01; 8160ExxB_r1_02 8160ExxB_r1_02; 8160ExxB_r1_03 Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • ...

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