GS816018T-225 GSI [GSI Technology], GS816018T-225 Datasheet

GS816018T-225

Manufacturer Part Number

GS816018T-225

Description

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS816018T-225.pdf (28 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Functional Description

Applications

The GS816018/32/36T is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Rev: 2.12 3/2002

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Through

Pipeline

operation

3-1-1-1

2-1-1-1

3.3 V

2.5 V

Flow

3.3 V

2.5 V

Curr

tCycle

(x32/x36)

(x18)

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

5.5

255

300

250

295

165

190

165

190

2.7

4.4

6.0

1M x 18, 512K x 32, 512K x 36

230

270

230

265

160

180

160

180

3.0

5.0

6.5

18Mb Sync Burst SRAMs

200

230

195

225

150

170

150

170

3.4

6.0

7.0

185

215

180

210

145

165

145

165

3.8

6.7

7.5

165

190

165

185

135

150

135

150

4.0

7.5

8.5

1/28

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS816018/32/36T operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

GS816018/32/36T-250/225/200/166/150/133

DDQ

) pins are used to decouple output noise

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

Related parts for GS816018T-225

GS816018T-225 Summary of contents

Page 1

TQFP Commercial Temp 18Mb Sync Burst SRAMs Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2 ...

Page 2

GS816018 100-Pin TQFP Pinout 100 DDQ ...

Page 3

GS816032 100-Pin TQFP Pinout 100 DDQ ...

Page 4

GS816036 100-Pin TQFP Pinout 100 DDQ ...

Page 5

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, ...

Page 6

GS816018/32/36 Block Diagram Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only ...

Mode Pin Functions Mode Name Name Burst Order Control Output Register Control Power Down Control Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and ...

Page 8

Byte Write Truth Table Function GW BW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs ...

Page 9

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst ...

Page 10

Simplified State Diagram X Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) ...

Page 11

Simplified State Diagram with G X Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to ...

Page 12

Absolute Maximum Ratings ) (All voltages reference Symbol V Voltage Voltage in V DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other Input Pins ...

Page 13

Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3 I/O Supply Voltage DDQ 2 I/O Supply Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character ...

Page 14

Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case ...

Page 15

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 16

Rev: 2.12 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816018/32/36T-250/225/200/166/150/133 16/28 Preliminary © 1999, Giga Semiconductor, Inc. ...

Page 17

AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid tKQX Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid tKQX Flow ...

Page 18

Write Cycle Timing Single Write ADSP ADSC ADV – 0 WR1 – Hi-Z DQ ...

Page 19

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV – RD1 – ...

Page 20

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV – RD1 – ...

Page 21

Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV – RD1 – ...

Page 22

Pipelined SCD Read-Write Cycle Timing Single Read ADSP ADSC ADV – 0 RD1 – ...

Page 23

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 24

TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...

Page 25

... GS816036T-250 512K x 36 GS816036T-225 512K x 36 GS816036T-200 512K x 36 GS816036T-166 512K x 36 GS816036T-150 512K x 36 GS816036T-133 GS816018T-250I GS816018T-225I GS816018T-200I GS816018T-166I GS816018T-150I GS816018T-133I 512K x 32 GS816032T-250I 512K x 32 GS816032T-225I 512K x 32 GS816032T-200I 512K x 32 ...

Page 26

... GS816036T-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 27

... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content GS816018T-150IT 1.00 9/ 1999A;GS816018T-150IT 2.00 1/1999B GS816018T- 2.00 11/ 1999B;GS816018T 2.01 1/ 2000C GS816018T 2.01 1/ 2000C;GS816018 T 2.02 1/ 2000D GS18/362.0 1/2000DGS18/ 362.03 2/2000E GS18/362.03 2/2000E; 816018_r2_04 816018_r2_04; 816018_r2_05 816018_r2_05; Content/Format 816018_r2_06 816018_r2_06; 816018_r2_07 816018_r2_07; 816018_r2_08 816018_r2_08; ...

Page 28

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 816018_r2_09; 816018_r2_10 816018_r2_10; 816018_r2_11 816018_r2_11; 816018_r2_12 Rev: 2.12 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816018/32/36T-250/225/200/166/150/133 Page;Revisions;Reason ...

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