MACH5 Lattice, MACH5 Datasheet
MACH5
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MACH5 Summary of contents
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... Flexibility to adapt to user requirements — Software partnerships that ensure customer success Lattice and Third-party hardware programming support — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, ...
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Feature Supply Voltage (V) Macrocells 128 Maximum User I/O Pins 120 t (ns (ns (ns) COS f (MHz) 182 CNT Typical Static Power (mA) IEEE 1149.1 Boundary Scan Compliant PCI-Compliant Note: 1. “M5-xxx” is for 5-V ...
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... Extensive routing resources ensure pinout retention as well as high utilization ideal for PAL of other applications including high-speed computing, low-power applications, communications, and embedded control. At each macrocell density point, Lattice offers several I/O and package options to meet a wide range of design needs (Table 3). Table 3. MACH 5 Package and I/O Options ...
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Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system programmable ...
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Block Feeder Product-Term Array and Logic Allocator The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters . A cluster is a sum- ...
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Macrocells The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be configured as T-type, J-K, or S-R operation through the use of ...
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Clock Line 1 Options Global clock ( with positive edge clock enable Global clock ( with negative edge clock enable Global clock ( with positive and negative edge ...
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OE Generator There is one output enable (OE) generator per PAL block that generates two product-term driven output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can choose to be permanently enabled, ...
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MACH 5 TIMING MODEL The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and ...
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... Boundary Scan chain, and creates a set of vectors that are used to drive the Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equipment can then be used to program MACH 5 devices during the testing of a circuit board ...
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... At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power tradeoff can be tailored for each design ...
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V rise must be monotonic and the clock must be inactive until the reset CC delay time has elapsed. SECURITY BIT A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized ...
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MACH 5 PAL BLOCK Switch Matrix Control Generator ...
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BLOCK DIAGRAM — M5(LV)-128/XXX Block A/Macrocells 0-15 16 I/O Cells 2 Macrocells Macrocells 2 I/O Cells 16 Block B/Macrocells 0-15 CLK0 CLK1 CLK2 4 CLK3 SEGMENT 0 Block D/Macrocells ...
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BLOCK DIAGRAM — M5-192/XXX MACH 5 Family 20446G-008 15 ...
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BLOCK DIAGRAM — M5(LV)-256/XXX 16 MACH 5 Family 20446G-009 ...
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BLOCK DIAGRAM — M5(LV)-320/XXX MACH 5 Family 20446G-010 17 ...
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BLOCK DIAGRAM — M5(LV)-384/XXX 18 MACH 5 Family 20446G-011 ...
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BLOCK DIAGRAM — M5(LV)-512/XXX Continued MACH 5 Family 20446G-012 19 ...
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BLOCK DIAGRAM — M5(LV)-512/XXX 20 Continued MACH 5 Family 20446G-013 ...
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ABSOLUTE MAXIMUM RATINGS M5 Storage Temperature . . . . . . . . . . . . . .- +150 C Device Junction Temperature (Note ...
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ABSOLUTE MAXIMUM RATINGS M5LV Storage Temperature . . . . . . . . . . . . . .- +150 C Device Junction Temperature . . . . . . . . . . . . . ...
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M5(LV) TIMING PARAMETERS OVER OPERATING RANGES Combinatorial Delay: Internal combinatorial propagation t PDi delay t Combinatorial propagation delay PD Registered Delays: t Synchronous clock setup time SS t Asynchronous clock setup time SA t Synchronous clock hold time HS t ...
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M5(LV) TIMING PARAMETERS OVER OPERATING RANGES Power Delays: t Power level 1 delay (Note 2) PL1 t Power level 2 delay (Note 2) PL2 t Power level 3 delay (Note 2) PL3 Additional Cluster Delay: t Product term cluster delay ...
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... SIRS HIRS WICW Notes: 1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site. 2. Numbers in parentheses are for M5-128, M5-192, M5-256 signal is used as both a clock and a logic array input, then the maximum input frequency applies (f -5 ...
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... The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book CD-ROM or Lattice web site. ...
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M5-256 low power M5-192 low power 100 M5-128 low power 0 Figure 25º M5-128 high power Frequency (MHz) Curves at High/Low Power Modes ...
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PQFP CONNECTION DIAGRAM Top View M5-128 M5LV-128* M5-192* M5-256* M5LV-256 GND GND TDI 0A14 0A12 0A12 I/O0 0B13 0B13 0B13 I/O1 0B12 0B12 0B12 I/O2 0B11 0B11 0B11 I/O3 0B8 0B8 0B8 I/O4 0B7 0B7 0B7 I/O5 0B4 0B4 ...
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TQFP CONNECTION DIAGRAM – 68 I/O Top View M5-128 M5LV-128 M5-192 M5-256 M5LV-256* TDI 1 0A14 0A12 0A12 I/O0 2 0B13 0B13 0B13 I/O1 3 0B12 0B12 0B12 I/O2 4 0B11 0B11 0B11 I/O3 5 0B8 0B8 0B8 I/O4 ...
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TQFP CONNECTION DIAGRAM – 74 I/O Top View M5LV-128 M5LV-256 TDI 1 0A14 0A12 I/O0 2 0B13 0B13 I/O1 3 0B12 0B12 I/O2 4 0B11 0B11 I/O3 5 0B8 0B8 I/O4 6 0B7 0B7 I/O5 7 0B4 0B4 I/O6 ...
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PQFP CONNECTION DIAGRAM Top View M5-128 M5LV-128* M5-192* M5-256* M5LV-256* TDI 1 0A14 0A12 0A8 I/O0 2 0B13 0A13 0A9 I/O1 3 0B12 0A14 0A10 I/O2 4 0B11 0B13 0A11 I/O3 5 0B10 0B12 0A12 I/O4 6 GND 7 ...
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TQFP CONNECTION DIAGRAM Top View M5LV-128 M5LV-256 TDI 1 0A14 0A8 I/O0 2 0B13 0A9 I/O1 3 0B12 0A10 I/O2 4 0B11 0A11 I/O3 5 0B10 0A12 I/O4 6 GND 7 0B8 0B13 I/O5 8 0B7 0B12 I/O6 9 ...
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PQFP CONNECTION DIAGRAM Top View M5-128 M5LV-128 M5-192 M5-256 M5LV-256 TDI 1 0A14 0A12 0A8 I/O0 2 0A15 0A13 0A9 I/O1 3 0B14 0A14 0A10 I/O2 4 0B13 0A15 0A11 I/O3 5 0B12 0B15 0A12 I/O4 6 0B11 0B14 ...
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PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM Top View M5-320* M5LV-320 M5-384* M5LV-384 M5-512* M5LV-512 TDI 1 0A2 0A2 0A2 I/O0 2 0A3 0A3 0A3 I/O1 3 0A4 0A4 0A4 I/O2 4 0A7 0A7 0A7 I/O3 5 0A8 0A8 ...
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PQFP CONNECTION DIAGRAM Top View M5-256 M5LV-256 TDI 1 0A8 I/O0 2 0A9 I/O1 3 0A10 I/O2 4 0A11 I/O3 5 0A12 I/O4 6 0A13 I/O5 7 0A14 I/O6 8 0A15 I/ GND 11 0B13 ...
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PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM Top View M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 TDI 1 0A2 0A2 0A2 I/O0 2 0A3 0A3 0A3 I/O1 3 0A4 0A4 0A4 I/O2 4 0A7 0A7 0A7 I/O3 5 0A8 0A8 ...
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PQFP CONNECTION DIAGRAM Top View M5-320* M5LV-320* M5-384* M5LV-384* M5-512* M5LV-512* TDI 1 0A2 0A2 0A2 I/O0 2 0A3 0A3 0A3 I/O1 3 0A4 0A4 0A4 I/O2 4 0A7 0A7 0A7 I/O3 5 0A8 0A8 0A8 I/O4 6 0A11 ...
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BGA CONNECTION DIAGRAM — M5-320, M5LV-320*, M5-384*, M5LV-384*, M5-512*, M5LV-512* Bottom View (I/O Pin-outs) *Package obsolete, contact factory. 38 256-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect ...
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BGA CONNECTION DIAGRAM — M5-320, M5LV-320* Bottom View (Macrocell Association) *Package obsolete, contact factory. 256-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC ...
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BGA CONNECTION DIAGRAM — M5-384*, M5LV-384* Bottom View (Macrocell Association) *Package obsolete, contact factory. 40 256-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage ...
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BGA CONNECTION DIAGRAM — M5-512*, M5LV-512* Bottom View (Macrocell Association) *Package obsolete, contact factory. 256-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC ...
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BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 42 352-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC TDI = Test ...
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BGA CONNECTION DIAGRAM — M5-512, M5LV-512 Bottom View (I/O Pin-outs) 352-Ball BGA Pin Designations CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC TDI = Test Data ...
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... M5 ORDERING INFORMATION Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. . FAMILY TYPE M5- = MACH 5 (5 MACROCELL DENSITY 128 = 128 Macrocells 192 = 192 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells ...
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... M5LV ORDERING INFORMATION Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. FAMILY TYPE M5LV- = MACH 5 Low Voltage (3.3 MACROCELL DENSITY 128 = 128 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells ...
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MACH 5 Family, 3.3-V Ind ...
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MACH 5 Family, 3.3-V Ind 47 ...