K6T4008C1C-DB55 Samsung semiconductor, K6T4008C1C-DB55 Datasheet - Page 7

• Manufacturer Part Number: K6T4008C1C-DB55
• Description: 512Kx8 bit Low Power CMOS Static RAM
• Manufacturer: Samsung semiconductor

DATA RETENTION WAVE FORM
K6T4008C1C Family
TIMING WAVEFORM OF WRITE CYCLE(1)
TIMING WAVEFORM OF WRITE CYCLE(2)
CS controlled
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
2. t
3. t
4. t
Address
CS
WE
Data in
Data out
Address
CS
WE
Data in
Data out
V
4.5V
2.2V
V
CS
GND
CC
DR
going low : A write end at the earliest transition among CS going high and WE going high, t
to the end of write.
CW
AS
WR
is measured from the CS going low to end of write.
is measured from the address valid to the beginning of write.
is measured from the end of write to the address change. t
Data Undefined
High-Z
t
SDR
t
t
AS(3)
AS(3)
(CS Controlled)
(WE Controlled)
WR
Data Retention Mode
t
WHZ
t
AW
7
applied in case a write ends as CS or WE going high.
t
CS V
AW
t
t
WC
CW(2)
t
CW(2)
t
WC
t
t
CC
WP(1)
WP(1)
- 0.2V
t
t
DW
DW
Data Valid
Data Valid
WP
is measured from the begining of write
t
t
WR(4)
WR(4)
t
t
DH
DH
t
OW
High-Z
t
RDR
CMOS SRAM
Revision 1.0
April 1999