HYS64D16000GDL-6-B Infineon, HYS64D16000GDL-6-B Datasheet - Page 22

• Manufacturer Part Number: HYS64D16000GDL-6-B
• Description: 200-Pin Small Outline Dual-In-Line Memory Modules
• Manufacturer: Infineon

1) 0 C
2) Input slew rate
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
13) For each of the terms, if not already an integer, round to the next highest integer.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
level for signals other than CK/CK, is
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
ns, measured between
t
cycle time.
HZ
RPRES
and
T
is defined for CL = 1.5 operation only
A
t
LZ
70 C;
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
1.0 V/ns , slow slew rate
1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
V
DDQ
V
= 2.5 V 0.2 V,
OH(ac)
and
V
OL(ac)
V
REF
V
V
REF
DD
. CK/CK slew rate are
.
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
= +2.5 V 0.2 V
stabilizes.
22
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
1.0 V/ns.
Small Outline DDR SDRAM Modules
t
CK
is equal to the actual system clock
t
DQSS
.
AC Characteristics
V1.2, 2003-08
V
TT
.