HYS64D128021HBDL-5-B Infineon, HYS64D128021HBDL-5-B Datasheet - Page 17

• Manufacturer Part Number: HYS64D128021HBDL-5-B
• Description: 200-Pin Small Outline Dual-In-Line Memory Modules
• Manufacturer: Infineon

Table 10
Parameter
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
Data Sheet
(DDR400)
level for signals other than CK/CK, is
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
HZ
and
T
t
A
LZ
AC Timing - Absolute Specifications –6/–5 (cont’d)
≤ 70 °C
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
; V
DDQ
= 2.5 V ± 0.2 V,
V
REF
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
REF
IS
IH
RPRE
RPST
RAS
RC
RFC
RCD
RP
RAP
RRD
WR
DAL
WTR
XSNR
XSRD
REFI
V
. CK/CK slew rate are ≥ 1.0 V/ns.
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
Min.
0.75
0.8
0.75
0.8
0.9
0.40
42
60
72
18
18
18
12
15
1
75
200
—
17
DDR333B
–6
Max.
—
—
—
—
1.1
0.60
70E+3
—
—
—
—
—
—
—
—
—
—
7.8
Small Outline DDR SDRAM Modules
HYS64D128021[H/G]BDL–[5/6]–B
Min.
0.6
0.7
0.6
0.7
0.9
0.40
40
55
65
15
15
15
10
15
1
75
200
—
V
DDQ
DDR400B
= 2.6 V ± 0.1 V,
–5
Max.
—
—
—
—
1.1
0.60
70E+3
—
—
—
—
—
—
—
—
—
—
7.8
t
DQSS
Electrical Characteristics
Unit
ns
ns
ns
ns
t
t
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ns
t
µs
.
CK
CK
CK
CK
CK
V
DD
Rev. 0.5, 2003-12
= +2.6 V ± 0.1 V
fast slew rate
slow slew
fast slew rate
slow slew
Note/ Test
Condition
3)4)5)6)10)
rate
3)4)5)6)10)
3)4)5)6)10)
rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
V
1)
TT
.