HYS64-74V8200GU Siemens, HYS64-74V8200GU Datasheet - Page 14

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HYS64-74V8200GU

Manufacturer Part Number
HYS64-74V8200GU
Description
3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
Manufacturer
Siemens
Datasheet
SPD-Table for PC100 Modules (cont’d)
Byte# Description
29
30
31
32
33
34
35
62-61 Superset
62
63
64-
125
126
127
128+
Semiconductor Group
Minimum RAS to
CAS delay
Minimum RAS
pulse width
Module Bank
Density (per bank)
SDRAM input setup
time
SDRAM input hold
time
SDRAM data input
hold time
SDRAM data input
setup time
information (may
be used in future)
SPD Revision
Checksum for
bytes 0 - 62
Manufacturers
information
(optional)
(FF
Frequency
Specification
100 MHz support
details
Unused storage
locations
H
if not used)
t
t
RCD
RAS
SPD
Entry
Value
20 ns
45 ns
64 MByte
2 ns
1 ns
2 ns
1 ns
Revision
1.2
100 MHz
14
2D
10
20
10
20
10
FF
12
D8
XX
64
AF
FF
8M 64
-8
14
8M 64
14
2D
10
20
10
20
10
FF
12
16
XX
64
AD
FF
-8B
HYS 64(72)V8200/16220GU-8/-10
14
2D
10
20
10
20
10
FF
12
EA
XX
64
AF
FF
8M 72
-8
Hex
16M 64
14
2D
10
20
10
20
10
FF
12
D9
XX
64
FF
FF
-8
SDRAM Modules
16M 64
14
2D
10
20
10
20
10
FF
12
17
XX
64
FD
FF
-8B
1998-08-01
14
2D
10
20
10
20
10
FF
12
EB
XX
64
FF
FF
16M 72
-8

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