HYS64-74V8200GU Siemens, HYS64-74V8200GU Datasheet - Page 13

• Manufacturer Part Number: HYS64-74V8200GU
• Description: 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
• Manufacturer: Siemens

SPD-Table for PC100 Modules (cont’d)
Byte# Description
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Semiconductor Group
Minimum clock
delay for back-to-
back random
column address
Burst Length
supported
Number of SDRAM
banks
Supported CAS
Latencies
CS Latencies
WE Latencies
SDRAM DIMM
module attributes
SDRAM Device
Attributes: General
Min. Clock Cycle
Time at CAS
Latency = 2
Max. data access
time from Clock for
CL = 2
Minimum Clock
Cycle Time at
CL = 1
Maximum Data
Access Time from
Clock at CL = 1
Minimum Row
Precharge Time
Minimum Row
Active to Row
Active delay
t
RRD
SPD
Entry
Value
t
CLK
1, 2, 4, 8 &
full page
4
CAS
latency =
2 & 3
CS
latency = 0
Write
latency = 0
non
buffered/
non reg.
V
10%
10.0/12.0
ns
6.0/7.0 ns
not
supported
not
supported
20/30 ns
16/20 ns
CCD
CC
tol
= 1
01
8F
04
06
01
01
00
06
A0
60
FF
FF
14
10
8M 64
-8
13
8M 64
01
8F
04
06
01
01
00
06
C0
70
FF
FF
1E
14
-8B
HYS 64(72)V8200/16220GU-8/-10
01
8F
04
06
01
01
00
06
A0
60
FF
FF
14
10
8M 72
-8
Hex
16M 64
01
8F
04
06
01
01
00
06
A0
60
FF
FF
14
10
-8
SDRAM Modules
16M 64
01
8F
04
06
01
01
00
06
C0
60
FF
FF
1E
14
-8B
1998-08-01
01
8F
04
06
01
01
00
06
A0
60
FF
FF
14
10
16M 72
-8