HI-8686 Holt Integrated Circuits, HI-8686 Datasheet - Page 2

• Manufacturer Part Number: HI-8686
• Description: (HI-8685 / HI-8686) ARINC INTERFACE DEVICE ARINC 429 & 561 SERIAL DATA TO 16-BIT PARALLEL DATA
• Manufacturer: Holt Integrated Circuits

PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
The HI-8685 and HI-8686 are serial to 16-bit parallel convert-
ers. The incoming data stream is serially shifted into an input
register, checked for errors, and then transferred in parallel to
a 32-bit receive buffer. The receive data can be accessed us-
ing two 16-bit parallel read operations while the next serial
data steam is being received.
RECEIVER INPUTS
The block diagram for both the HI-8685 and HI-8685-10 prod-
ucts is found in Figure 1. Both have built-in receivers elimi-
nating the need for additional external ARINC level detection
circuitry. The only difference between the two products is the
amount of internal resistance in series with each ARINC in-
put.
HI-8685 ARINC INPUTS (RINA & RINB)
Typically 35K resistors are in series with both the RINA and
RINB ARINC 429 inputs. They connect to level translators
whose resistance to GND is typically 10K
RINA/RINA-10
RINB/RINB-10
PARITY ENB
DATA RDY
D0 to D15
GAPCLK
SIGNAL
ERROR
RESET
TESTA
TESTB
READ
GND
Vcc
FUNCTION
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Receiver data ready flag. A high level indicates data is available in the receive
buffer. Flag goes low when the first 16-bit byte is read.
16-bit parallel data bus (tri-state)
0V
Read strobe. A low level transfers receive buffer data to the data bus
Parity Enable - A high level activates odd parity checking which replaces the
32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged
Error Flag. A high level indicates a bit count error (number of ARINC bits was
less than or greater than 32) and/or a parity error if parity detection was enabled
(PARITY ENB high)
Positive direct ARINC serial data input
Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686)
Internal logic states are initialized with a low level
Used in conjunction with the TESTB input to bypass the built-in analog line
receiver circuitry
U
receiver circuitry
Gap Clock. Determines the minimum time required between ARINC words for
detection. The minimum word gap time is between 16 and 17 clock cycles of
this signal.
+5V ±10% supply
sed in conjunction with the TESTA input to bypass the built-in analog line
After level trans-
HOLT INTEGRATED CIRCUITS
HI-8685, HI-8686
2
lation, the buffered inputs drive a differential amplifier. The
differential signal is compared to levels derived from a divider
between VCC and GND. The nominal settings correspond to
a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A
valid ARINC One/Zero input sets a latch and a Null input re-
sets the latch.
HI-8685-10 ARINC INPUTS (RINA-10 & RINB-10)
Since any added external series resistance will affect the volt-
age translation, the HI-8685-10 product has only 25K
the 35K
level detection. The remaining 10K required is available to
the user for incorporation in external circuitry such as for
lightning protection.
HI-8686 ARINC INPUTS
The HI-8686 has both sets of ARINC inputs, RINA/RINA-10
and RINB/RINB-10 available to the user.
DESCRIPTION
series resistance required for proper ARINC 429
(both RINA and RINA-10 on HI-8686)
of