AM79C972BKCW Advanced Micro Devices, AM79C972BKCW Datasheet - Page 120

• Manufacturer Part Number: AM79C972BKCW
• Description: PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
• Manufacturer: Advanced Micro Devices

CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-0
CSR13: Physical Address Register 1
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-0
120
Name
RES
PADR[15:0] Physical
Name
RES
PADR[31:16]Physical
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
write has been performed on this
register.
Description
Reserved locations. Written as
zeros and read as undefined.
PADR[15:0]. The contents of this
register are loaded from EE-
PROM after H_RESET or by an
EEPROM
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Description
Reserved locations. Written as
zeros and read as undefined.
PADR[31:16]. The contents of
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
Address
Address
read
read
command
command
Register,
Register,
Am79C972
CSR14: Physical Address Register 2
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
CSR15: Mode
This register’s fields are loaded during the Am79C972
controller initialization routine with the corresponding
Initialization Block values, or when a direct register write
has been performed on this register.
Bit
31-16 RES
15
Name
PADR[47:32]Physical
Name
PROM
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
PADR[47:32].The
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
PROM = 1, all incoming receive
frames are accepted.
This register can also be loaded
Description
Reserved locations. Written as
This register can also be loaded
Description
Reserved locations. Written as
Promiscuous
Address
read
Mode.
contents
command
Register,
When
of