AM79C972 Advanced Micro Devices, AM79C972 Datasheet
AM79C972
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AM79C972 Summary of contents
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... Am79C972 PCnet™-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support DISTINCTIVE CHARACTERISTICS n Integrated Fast Ethernet controller for the Peripheral Component Interconnect (PCI) bus — 32-bit glueless PCI host interface — Supports PCI clock frequency from MHz independent of network clock — ...
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... PCs and bridge/router designs. The bus master architecture provides high data throughput and low CPU and sys- tem bus utilization. The Am79C972 controller is fabri- cated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive ap- plications ...
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... In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, link integrity, Magic Packet status, activity, address match, full-du- plex, or 100 Mbps status. The Am79C972 controller also provides an EADI to allow external hardware ad- dress filtering in internetworking applications and a re- ceive frame tagging feature. ...
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... SRAM Core Bus MAC Xmt Xmt FIFO FIFO Network FIFO Port Control Manager OnNow Power Management Unit PME PG RWU WUMI Am79C972 TXEN TXCLK TXDAT GPSI RXEN Port RXCLK RXDAT CLSN TX_ER TXD[3:0] TX_EN TX_CLK COL MII RXD[3:0] Port RX_ER RX_CLK RX_DV ...
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... TABLE OF CONTENTS AM79C972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DISTINCTIVE CHARACTERISTICS1 GENERAL DESCRIPTION2 TABLE OF CONTENTS RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 CONNECTION DIAGRAM (PQR160)8 PIN DESIGNATIONS (PQR160 .10 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PIN DESIGNATIONS (PQL176 .11 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PIN DESIGNATIONS (PQR160, PQL176 .12 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Standard Products ...
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... Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 Am79C972 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS: BUS INTERFACE ...
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... PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support) Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses) Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Ethernet Controller for PCI Local Bus Am79C972 7 ...
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... AD14 33 AD13 34 VSSB 35 AD12 36 AD11 37 VDD_PCI 38 AD10 39 AD9 40 Pin 1 is marked for orientation. 8 PCnet“-FAST+ Am79C972BKC Am79C972 Am79C972 EEDO/LED3/SRD/MIIRXFRTGD 120 PHY_RST 119 118 MDIO VSSB 117 116 MDC 115 RXD3 RXD2 114 113 VDDB 112 RXD1 111 RXD0/RXFRTGD VSS 110 ...
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... AD14 36 AD13 37 VSSB 38 AD12 39 AD11 40 VDD_PCI 41 AD10 42 AD9 Pin 1 is marked for orientation. PCnet“-FAST+ Am79C972 Am79C972BVC Am79C972 132 NC 131 NC EEDO/LED3/SRD/MIIRXFRTGD 130 129 PHY_RST 128 MDIO 127 VSSB MDC 126 125 RXD3 124 RXD2 VDDB 123 122 RXD1 ...
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... RXD3 155 116 MDC 156 117 VSSB 157 118 MDIO 158 119 PHY_RST 159 EEDO/LED3/SRD/ 120 160 MIIRXFRTGD Am79C972 Pin Name EEDI/LED0 TBC_IN TBC_EN VDDB LED2/SRDCLK/ MIIRXFRTGE EESK/LED1/SFBD VSSB EECS EAR VSS PME WUMI RWU TCK TMS VDDB TDO ...
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... MDC 170 127 VSSB 171 128 MDIO 172 129 PHY_RST 173 EEDO/LED3/SRD/ 130 174 MIIRXFRTGD 131 NC 175 132 NC 176 Am79C972 Pin Name NC NC EEDI/LED0 TBC_IN TBC_EN VDDB LED2/SRDCLK/ MIIRXFRTGE EESK/LED1/SFBD VSSB EECS EAR VSS PME WUMI RWU TCK TMS VDDB ...
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... EBD[7:0] Expansion Bus Data [7:0] EBDA[15:8] Expansion Bus Data/Address [15:8] EBUA_EBA[7:0] Expansion Bus Upper Address /Expansion Bus Address [7:0] EBWE Expansion Bus Write Enable EROMCS Expansion Bus ROM Chip Select Note: 1. Not including test features. 12 Type Am79C972 1 No. of Pins ...
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... Test Data Out TMS Test Mode Select Power Supplies VDD Digital Power VSS Digital Ground VDDB I/O Buffer Power VSSB I/O Buffer Ground VDD_PCI PCI I/O Buffer Power Note: 1. Not including test features. 1 Type Am79C972 No. of Pins ...
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... Listed By Driver Type The following table describes the various types of out- put drivers used in the Am79C972 controller. All I I values shown in the table apply to 3.3 V signaling. OH Name Type LED LED OMII1 Totem Pole OMII2 Totem Pole O6 Totem Pole OD6 Open Drain ...
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... PCnet-FAST+ Enhanced 10/100 Mbps PCI Ether- net Controller with OnNow Support Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local KC\W, AMD sales office to confirm availability of specific VC\W valid combinations and to check on newly released combinations. KI\W, VI\W Am79C972 15 ...
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... When RST is active, GNT is an input for NAND tree testing. IDSEL Initialization Device Select Input This signal is used as a chip select for the Am79C972 controller during configuration read and write transac- tions. When RST is active, IDSEL is an input for NAND tree testing. ...
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... IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock when both IRDY and TRDY are asserted. When the Am79C972 controller is a bus master, it as- serts IRDY during all write data phases to indicate that valid data is present on AD[31:0]. During all read data phases, the device asserts IRDY to indicate that it is ready to accept the data ...
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... AD[31:0]. During all write data phases, the device checks TRDY to determine if the target is ready to accept the data. When the Am79C972 controller is the target of a trans- action, it asserts TRDY during all read data phases to indicate that valid data is present on AD[31:0]. During all write data phases, the device asserts TRDY to indi- cate that it is ready to accept the data ...
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... SFBD pins. The LED1 pin is also used during EEPROM Auto- Detection to determine whether or not an EEPROM is present at the Am79C972 controller interface. At the last rising edge of CLK while RST is active LOW, LED1 is sampled to determine the value of the EEDET bit in BCR19 important to maintain adequate hold time around the rising edge of the CLK at this time to ensure a correctly sampled value ...
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... EEPROM that uses the 93C46 EEPROM interface pro- Input tocol. EESK is connected to the EEPROM’s clock pin controlled by either the Am79C972 controller di- rectly during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 1. Note: The EESK pin is multiplexed with the LED1 and SFBD pins ...
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... TX_CLK is a continuous clock input that provides the timing reference for the transfer of the TX_EN, Input/Output TXD[3:0], and TX_ER signals out of the Am79C972 device. TX_CLK must provide a nibble rate clock (25% of the network data rate). Hence, an MII transceiver op- erating at 10 Mbps must provide a TX_CLK frequency of 2 ...
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... RX_DV is an input used to indicate that valid received data is being presented on the RXD[3:0] pins and RX_CLK is synchronous to the receive data. In order for a frame to be fully received by the Am79C972 de- vice on the MII, RX_DV must be asserted prior to the RX_CLK rising edge, when the first nibble of the Start ...
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... The RX_CLK Output should be used in conjunction with the SFBD to latch the correct data for external address matching. SFBD will be active only during frame reception. Note: The SFBD pin is multiplexed with the EESK and LED1 pins. Am79C972 Input 5% resistor. Output 23 ...
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... TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency MHz. TCK has an internal pull up resistor. TDI Test Data In TDI is the test data input path to the Am79C972 con- troller. The pin has an internal pull up resistor. Input TDO Test Data Out TDO is the test data output path from the Am79C972 controller ...
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... There are six power supply pins that are used by the in- ternal digital circuitry. All VDD pins must be connected Power to a +3.3 V supply. VSS Digital Ground (8 Pins) There are eight ground pins that are used by the inter- nal digital circuitry. Am79C972 Power Power Power 25 ...
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... Am79C972 controller interrupt chan- nel. This allows for a jumperless implementation. The second portion of the software interface is the di- rect access to the I/O resources of the Am79C972 con- troller. The Am79C972 controller occupies 32 bytes of address space that must begin on a 32-byte block boundary ...
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... PCI configuration space, the Control and Status Registers (CSR), the Bus Configuration Registers (BCR), the Address PROM (APROM) locations, and the Expansion ROM. Table 2 shows the response of the Am79C972 controller to each of the PCI commands in slave mode. Table 2. Slave Commands C[3:0] Command ...
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... I/O resource is accessed. The typical number of wait states added to a slave I/O or memory mapped I/O read or write access on the part of the Am79C972 controller is six to seven clock cycles, depending upon the relative phases of the internal Buff- er Management Unit clock and the CLK signal, since 28 the internal Buffer Management Unit clock is a divide- by-two version of the CLK signal ...
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... IRDY TRDY DEVSEL STOP Figure 3. Slave Read Using I/O Command CLK FRAME AD ADDR 0111 C/BE PAR PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory Command DATA DATA BE PAR Am79C972 11 PAR 21485C 21485C-7 29 ...
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... The host must initialize the Expansion ROM Base Ad- dress register at offset 30H in the PCI configuration space with a valid address before enabling the access to the device. The Am79C972 controller will not react to any access to the Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Ex- pansion ROM Base Address register, bit 0) are set to 1 ...
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... AAH (byte 1). Slave Cycle Termination There are three scenarios besides normal completion of a transaction where the Am79C972 controller is the target of a slave cycle and it will terminate the access. Disconnect When Busy The Am79C972 controller cannot service any slave ac- cess while it is reading the contents of the EEPROM ...
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... If the host is not yet ready when the Am79C972 control- ler asserts TRDY, the device will wait for the host to as- sert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C972 controller will finish the first data phase by deasserting TRDY one clock later. ...
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... Bus Acquisition The Am79C972 microcode will determine when a DMA transfer should be initiated. The first step in any Am79C972 bus master transfer is to acquire ownership of the bus. This task is handled by synchronous logic within the BIU. Bus ownership is requested with the REQ signal and ownership is granted by the arbiter through the GNT signal ...
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... Basic Non-Burst Read Transfer By default, the Am79C972 controller uses non-burst cycles in all bus master read operations. All Am79C972 34 controller non-burst read accesses are of the PCI command type Memory Read (type 6). Note that during a non-burst read operation, all byte lanes will always be active ...
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... ADDR 1110 C/BE PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = ADDR DATA 0000 0110 PAR PAR DATA DATA DATA 0000 PAR PAR Am79C972 10 11 PAR 21485C-15 11 PAR 21485C-16 35 ...
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... BWRITE (BCR18, bit 5). To allow burst transfers in descriptor write operations, the Am79C972 controller must also be programmed to use SWSTYLE 3 (BCR20, bits 7-0). All Am79C972 control- ler burst write transfers are of the PCI command type Memory Write (type 7). AD[1:0] will both be 0 during the address phase indicating a linear burst order ...
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... EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ is not deasserted until the next to last data phase is fin- ished. Target Initiated Termination When the Am79C972 controller is a bus master, the cy- cles it produces on the PCI bus may be terminated by the target in one of three different ways: disconnect CLK ...
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... It finally releases the bus on clock 6. Since data integrity is not guaranteed, the Am79C972 controller cannot recover from a target abort event. The Am79C972 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI config- uration registers will not be cleared. Any on-going net- wor k transmission is ter minated in an order ly sequence ...
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... Preemption During Non-Burst Transaction When the Am79C972 controller performs multiple non- burst transactions, it keeps REQ asserted until the as- sertion of FRAME for the last transaction. When GNT is removed, the Am79C972 controller will finish the cur- rent transaction and then release the bus not the 3 4 ...
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... When it sees the PERR input asserted, the controller sets PERR (PCI Status register, bit 15 When PERREN (PCI Command register, bit 6) is set to 1, the Am79C972 controller also sets DATAPERR (PCI Status register, bit Am79C972 ...
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... Figure 19. Preemption During Non-Burst Transaction CLK FRAME AD ADDR DATA DATA C/BE 0111 PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 20. Preemption During Burst Transaction Am79C972 DATA BE PAR DATA DATA DATA BE PAR PAR PAR PAR 21485C-22 21485C-23 41 ...
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... PAR PERR IRDY TRDY DEVSEL Figure 22. Master Cycle Data Parity Error Response ADDR DATA 0111 0000 PAR DEVSEL is sampled Figure 21. Master Abort ADDR DATA 0111 BE PAR DEVSEL is sampled Am79C972 PAR 21485C- PAR 21485C-25 ...
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... SWSTYLE (BCR20, bits 7-0) must be set program the Am79C972 controller to use 32-bit software structures. The Am79C972 controller will react in the following way when a data parity error occurs: n Initialization block read: STOP (CSR0, bit 2) is set to 1 and causes a STOP_RESET of the device ...
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... Figure 24. Initialization Block Read In Burst Mode IADD i DATA IADD i +4 0110 0000 0110 PAR PAR CLK IADD i DATA 0110 0000 PAR PAR DEVSEL is sampled Am79C972 DATA 0000 PAR PAR 21485C- DATA PAR PAR 21485C-27 ...
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... During descriptor read accesses, the byte enable sig- nals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the Am79C972 controller will internally discard the extraneous informa- tion that was gathered during such a read. ...
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... DEVSEL REQ GNT Figure 26. Descriptor Ring Read In Burst Mode MD1 DATA MD0 0110 0000 0110 PAR PAR MD1 DATA DATA 0110 0000 PAR PAR DEVSEL is sampled Am79C972 DATA 0000 PAR PAR 21485C-28 7 PAR 21485C-29 ...
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... FIFO DMA Transfers Am79C972 microcode will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers of data to and from the Am79C972 FIFOs. Once the Am79C972 BIU has been granted bus mastership, it will perform a series of consecutive transfer cycles before relinquishing the bus. All trans- ...
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... GNT Figure 28. Descriptor Ring Write In Burst Mode MD2 DATA MD1 0111 0000 0111 PAR PAR MD2 DATA 0110 0000 PAR PAR DEVSEL is sampled Am79C972 DATA 0011 PAR PAR 21485C- DATA 0011 PAR 21485C-31 ...
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... The Am79C972 controller starts off by writ- ing only three bytes during the first data phase. This op- eration aligns the address for all other data transfers to a 32-bit boundary so that the Am79C972 controller can continue bursting full DWords receive buffer does not end on a DWord boundary, the Am79C972 controller will perform a non-DWord write on the last transfer to the buffer ...
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... CSR2 (most signifi- cant 16 bits of address). The host must write CSR1 and CSR2 before setting the INIT bit. The initialization block contains the user defined conditions for Am79C972 op- eration, together with the base addresses and length information of the transmit and receive descriptor rings. ...
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... Am79C972 controller sets the read-version of SPND to 1 and enters the suspend mode. In suspend mode, all of the CSR and BCR registers are accessible. As long as the Am79C972 controller is not reset while in sus- pend mode (by H_RESET, S_RESET setting the STOP bit), no re-initialization of the device is required after the device comes out of suspend mode ...
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... Am79C972 controller or the host. The OWN bit within the descriptor status information, either TMD or RMD, is used for this purpose. When OWN is set signifies that the Am79C972 controller currently has ownership of this ring descrip- tor and its associated buffer. Only the owner is permit- ted to relinquish ownership or to write to any field in the descriptor entry ...
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... Am79C972 controller does not own the current RDTE and the poll time has elapsed and RXON = 1 (CSR0, bit 5 Am79C972 controller does not own the next RDTE and there is more than one receive descriptor in the ring and the poll time has elapsed and RXON = 1. ...
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... PADR[47:32] LADRF[31:0 LADRF[63:32] RDRA[31:0] TDRA[31:0] If RXON is cleared to 0, the Am79C972 controller will never poll RDTE locations. In order to avoid missing frames, the system should have at least one RDTE available. To minimize poll ac- tivity, two RDTEs should be available. In this case, the poll operation will only consist of the check of the status of the current TDTE ...
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... OWN bit has a 0 value, the Am79C972 controller will resume incrementing the poll time counter. If the trans- mit descriptor OWN bit has a value of 1, the Am79C972 controller will begin filling the FIFO with transmit data and initiate a transmission. This end-of-operation poll ...
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... SRAM (SRAM SIZE in BCR 25, bits 7-0) is en- 56 abled through the Receive Frame Queuing mecha- nism. When the SRAM SIZE = 0, then the Am79C972 controller reverts back to the PCnet PCI II mode of op- eration. This operation is automatic and does not re- quire any programming by the host. When SRAM is ...
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... SFD) have been received, the MAC engine will automatically delete the frame from the receive FIFO, without host intervention. The Am79C972 controller has the ability to accept runt packets for diagnostic purposes and proprietary net- works. Destination Address Handling The first 6 bytes of information after SFD will be inter- preted as the destination address field ...
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... See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1: Note possible for the PLS carrier sense indication to fail to be asserted during a collision on the media. If the deference process simply times the inter-Frame gap based on this indication possible for a short in- terFrame gap to be generated, leading to a potential Am79C972 ...
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... Am79C972 controller possi- bly capturing the network at times by forcing other less aggressive compliant nodes to defer. By programming a larger number of bit times, the Am79C972 MAC will become less aggressive on the network and may defer more often than normal. The performance of the ...
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... Transmit Operation The transmit operation and features of the Am79C972 controller are controlled by programmable options. The Am79C972 controller offers a large transmit FIFO to provide frame buffering for increased system latency, automatic retransmission with no FIFO reload, and au- tomatic transmit padding. ...
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... DXMTFCS is 0 after H_RESET. defined in the ISO 8802-3 (IEEE/ANSI 802.3) stan- dard). The length value contained in the message is not used by the Am79C972 controller to compute the ac- tual number of pad bytes to be inser ted. The Am79C972 controller will append pad bytes dependent on the actual number of bits transmitted onto the net- work ...
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... FIFO can be overwritten as soon transmitted total attempts (initial attempt plus 15 retries) fail, the Am79C972 controller sets the RTRY bit in the cur- rent transmit TDTE in host memory (TMD2), gives up ownership (resets the OWN bit to 0) for this frame, and processes the next frame in the transmit ring for trans- mission ...
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... LAFM (RMD1, bit 21) is set by the Am79C972 control- ler when it accepted the received frame based on the value in the logical address filter register. BAM (RMD1, bit 20) is set by the Am79C972 controller when it accepted the received frame because the frame’s destination address is of the type ’Broadcast’. ...
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... Figure 34. IEEE 802.3 Frame And Length Field Transmission Order Since any valid Ethernet Type field value will always be greater than a normal IEEE 802.3 Length field ( 46), the Am79C972 controller will not attempt to strip valid Ethernet frames. Note that for some network protocols, the value passed in the Ethernet Type and/or IEEE 802 ...
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... Retry error. General Purpose Serial Interface The General Purpose Serial Interface (GPSI) provides a direct interface to the MAC section of the Am79C972 controller. All signals are digital and data is non-en- coded. The GPSI allows use of an external Manchester encoder/decoder such as the Am7992B Serial Inter- face Adapter (SIA) ...
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... The SQE test function is disabled. n Loss of Carrier (LCAR) reporting is disabled. Full-Duplex Link Status LED Support The Am79C972 controller provides bits in each of the LED Status registers (BCR4, BCR5, BCR6, BCR7) to display the Full-Duplex Link Status. If the FDLSE bit (bit 8) is set, a value of 1 will be sent to the associated LED- OUT bit when in Full-Duplex ...
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... MDIO). See Figure 35. MII Transmit Interface The MII transmit clock is generated by the external PHY and is sent to the Am79C972 controller on the TX_CLK input pin. The clock can run at 25 MHz or 2.5 MHz, depending on the speed of the network to which the external PHY is attached. The data is a nibble-wide ...
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... Figure 36. Frame Format at the MII Interface Connection This is followed by a start field (ST) and an operation field (OP). The operation field (OP) indicates whether the Am79C972 controller is initiating a read or write op- eration. This is followed by the external PHY address (PHYAD) and the register address (REGAD) pro- grammed in BCR33. The PHY address of 1Fh is re- served and should not be used ...
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... MII Status register in the ex- ternal PHY. Network Port Manager The Am79C972 controller is unique in that it does not require software intervention to control and configure an external PHY attached to the MII. This was done to ensure backwards compatibility with existing software drivers ...
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... See Appendix C for the bit descriptions of the MII Status register. If the external PHY is Auto-Ne- gotiation capable and/or the XPHYANE (BCR32, bit 5) bit is set to 1, then the Am79C972 controller will start the external PHY’s Auto-Negotiation process. The Am79C972 controller will write to the external PHY’s ...
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... Am79C972 controller or the frame is of the type 'Broadcast', then the frame will be accepted regardless of the condition of EAR. When the EADISEL bit of BCR2 is set to 1 and the Am79C972 controller is programmed to promiscuous mode (PROM bit of the Mode Register is set to 1), then all in- coming frames will be accepted, regardless of any ac- tivity on the EAR pin ...
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... MII and the GPSI modes. The receive frame tagging implementation will be a two- and three-wire chip interface, respectively, added to the existing EADI. The Am79C972 controller supports bits of re- ceive frame tagging per frame in the receive frame sta- tus (RFRTAG). The RFRTAG bits are in the receive ...
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... The Am79C972 controller is function- ally equivalent to the PCnet-PCI II controller with Ex- pansion ROM. See Figure 40 and Figure 41. The Am79C972 controller will always read four bytes for every host Expansion ROM read access. The interface to the Expansion Bus runs synchronous to the PCI bus interface clock ...
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... AS_EBOE goes low. Next, the Am79C972 controller starts driving the lower 8 bits of the Expansion ROM address on EBUA_EBA[7:0]. The time that the Am79C972 controller waits for data to be valid is programmable. ROMTMG (BCR18, bits 15- 12) defines the time from when the Am79C972 control- ...
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... The timing diagram in Figure 42 assumes the default programming of ROMTMG (1001b = 9 CLK). After reading the first byte, the Am79C972 controller reads in three more bytes by incrementing the lower portion of the ROM address. After the last byte is strobed in, TRDY will be asserted on clock 50. When the host tries ...
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... PCI Memory Mapped I/O Base Address register, before enabling access to the Expansion ROM. The host must set the PCI Memory Mapped I/O Base Ad- dress register to a value that prevents the Am79C972 controller from claiming any memory cycles not in- tended for it. During the boot procedure, the system will try to find an Expansion ROM ...
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... EBAD- DRU. The Flash write is almost the same procedure as the read access, except that the Am79C972 controller will not drive AS_EBOE low. The EROMCS and EBWE are driven low for the value ROMTMG again. The write to ...
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... FLASH devices as long as there is no timing require- ment between the completion of commands. The FLASH access time cannot be guaranteed with the Am79C972 controller access mechanism. The Am79C972 controller will also support only Flash de- vices that do not require data hold times after write op- erations. Table 9. Am29Fxxx Flash Command ...
Page 79
... Am79C972 controller will configure itself for a low la- tency receive configuration. In this mode, SRAM is re- quired at all times. If the SRAM_SIZE (BCR25, bits 7- 0) value is 0, the Am79C972 controller will not config- ure for low latency receive mode. The Am79C972 con- troller will provide a fast path on the receive side bypassing the SRAM ...
Page 80
... Figure 46. Block Diagram Low Latency Receive Configuration 80 Bus MAC Rcv Rcv FIFO FIFO MAC Bus Xmt Xmt FIFO FIFO FIFO Control Bus MAC Rcv Rcv FIFO FIFO SRAM Bus MAC Xmt Xmt FIFO FIFO FIFO Control Am79C972 802.3 MAC Core 21485C-48 802.3 MAC Core 21485C-49 ...
Page 81
... EEPROM is present, and the EE- PROM read operation begins shortly after the RST pin is deasserted. If the sampled value of EESK/LED1/ SFBD the Am79C972 controller assumes that an external pulldown device is holding the EESK/LED1/ SFBD pin low, indicating that there is no EEPROM in the system ...
Page 82
... When an LED circuit is directly connected to the EEDO/LED3/SRD pin, then it is not possible for most EEPROM devices to sink enough I low level on the EEDO input to the Am79C972 control- ler. Use of buffering can be avoided if a low power LED is used. Each LED can be programmed through a BCR register ...
Page 83
... Reserved location: must be 00h Unused locations - Ignored by device 7Eh Reserved (active high). The output can be stretched to allow the human eye to recognize even short events that last only several microseconds. After H_RESET, the four LED outputs are configured as shown in Table 11. Am79C972 Least Significant Byte 83 ...
Page 84
... PME signal to be asserted. Assertion of the PME signal causes external hardware to wake up the CPU. The system software then reads the PMCSR reg- ister of every PCI device in the system to determine which device asserted the PME signal. Am79C972 To Pulse Stretcher 21485C-50 ...
Page 85
... PMR is programmed. When a pattern match has been detected, then PMAT bit (CSR116, bit 7) is set. The setting of the PMAT bit causes the Am79C972 WUMI MPINT LED MPMAT ...
Page 86
... Magic Packet frame can be unicast, multicast, or broadcast. Note: The setting of MPPLBA or EMPPLBA only ef- fects the address detection of the Magic Packet frame. The Magic Packet’s data sequence must be made consecutive copies of the device’s physical ad- dress (PADR[47:0]), regardless of what kind of destina- tion address it has. Am79C972 ...
Page 87
... PME_EN_OVR bits are set, then the PME will be asserted as well. If IENA (CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to 1, INTA will be asserted. Any one of the four LED pins can be programmed to indi- cate that a Magic Packet frame has been received. Am79C972 BCR PMR_B0 ...
Page 88
... All digital input, output, and input/output pins are tested. The following paragraphs summarize the IEEE 1149.1-compatible test functions imple- mented in the Am79C972 controller. Boundary Scan Circuit The boundary scan test circuit requires four pins (TCK, TMS, TDI, and TDO), defined as the Test Access Port (TAP) ...
Page 89
... Note: The content of the Device ID register is the same as the content of CSR88. NAND Tree Testing The Am79C972 controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit board. The NAND tree is built on all PCI bus, TBC_EN, and EAR pins. ...
Page 90
... STOP 29 25 PERR 30 26 SERR 31 28 PAR 32 30 C/BE1 33 31 AD15 34 33 AD14 0000FFFF 3 7 ... Figure 51. NAND Tree Waveform Am79C972 NAND Tree Input No. Pin No. Name 35 34 AD13 36 36 AD12 37 37 AD11 38 39 AD10 39 40 AD9 40 41 AD8 41 42 C/BE0 42 44 ...
Page 91
... H_RESET Hardware Reset (H_RESET Am79C972 reset operation that has been created by the proper asser- tion of the RST pin of the Am79C972 device while the PG pin is HIGH. When the minimum pulse width timing as specified in the RST pin description has been satis- fied, then an internal reset operation will be performed. ...
Page 92
... PCI configuration utility after system power-up. The PCI configuration utility must also set the IOEN bit in the PCI Command register to enable I/O accesses to the Am79C972 controller. For memory mapped I/O access, the PCI Memory Mapped I/O Base Address register controls the start address of the memory space ...
Page 93
... H_RESET or S_RESET. The RAP register will point to CSR0 at that time. Writing a value CSR0 is a safe operation. DWIO (BCR18, bit 7) will be set indication that the Am79C972 controller operates in 32-bit I/O mode. Note: Even though the I/O resource mapping changes when the I/O mode setting changes, the RDP location offset is the same for both modes ...
Page 94
... Table 20. Legal I/O Accesses in Double Word I/O AD[4:0] Register APROM RDP 0XX00 BDP) 10000 10100 BDP 11000 0XX00 10000 10100 11000 Am79C972 Comment Mode (DWIO =1) BE[3:0] Type Comment DWord read of APROM locations 3h (MSB 0000 RD (LSB 4h 0000 RD DWord read of RDP ...
Page 95
... USER ACCESSIBLE REGISTERS The Am79C972 controller has three types of user reg- isters: the PCI configuration registers, the Control and Status registers (CSR), and the Bus Control registers (BCR). The Am79C972 controller implements all PCnet-ISA (Am79C960) registers, all C-LANCE (Am79C90) regis- ters, plus a number of additional registers. The ...
Page 96
... Offset 02h The PCI Device ID register is a 16-bit register that uniquely identifies the Am79C972 controller within AMD's product line. The Am79C972 Device ID is 2000h. Note that this Device ID is not the same as the Part number in CSR88 and CSR89. The Device ID is assigned by AMD ...
Page 97
... Am79C972 con- troller. It controls the Am79C972 controller’s ability to generate and respond to PCI bus cycles. To logically disconnect the Am79C972 device from all PCI bus cy- cles except configuration cycles, a value of 0 should be written to this register. The PCI Command register is located at offset 04h in the PCI Configuration Space ...
Page 98
... PERR signal. PERR is not effected by the state of the Parity Error Response en- able bit (PCI Command register, bit 6). PERR is set by the Am79C972 controller and cleared by writing a 1. Writing a 0 has no effect. PERR is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. ...
Page 99
... Offset 09h The PCI Programming Interface register is an 8-bit reg- ister that identifies the programming interface of Am79C972 controller. PCI does not define any specific register-level programming interfaces for network devic- es. The value of this register is 00h. The PCI Programming Interface register is located at offset 09h in the PCI Configuration Space ...
Page 100
... Am79C972 controller is a single function device. 100 6-0 LAYOUT PCI I/O Base Address Register Offset 10h The PCI I/O Base Address register is a 32-bit register that determines the location of the Am79C972 I/O re- sources in all of I/O space located at offset 10h in the PCI Configuration Space. Bit Name 31-5 IOBASE 4-2 ...
Page 101
... I/O base address. PCI Memory Mapped I/O Base Address Register Offset 14h The PCI Memory Mapped I/O Base Address register is a 32-bit register that determines the location of the Am79C972 I/O resources in all of memory space located at offset 14h in the PCI Configuration Space. Bit Name Description 31-5 MEMBASE Memory mapped I/O base ad- dress most significant 27 bits ...
Page 102
... POST software has as- signed to the Am79C972 controller. The PCI Interrupt Line register is not modified by the Am79C972 control- ler. It has no effect on the operation of the device. The PCI Interrupt Line register is located at offset 3Ch in the PCI Configuration Space ...
Page 103
... Offset 3Dh This PCI Interrupt Pin register is an 8-bit register that indicates the interrupt pin that the Am79C972 controller is using. The value for the Am79C972 Interrupt Pin reg- ister is 01h, which corresponds to INTA. The PCI Interrupt Pin register is located at offset 3Dh in the PCI Configuration Space ...
Page 104
... Name 15 PME_STATUS PME Status. This bit is set when Initialization. 14-13 DATA_SCALE 12-9 DATA_SEL Data Select. This optional four-bit Am79C972 Specification Version. A value of 001b indicates that this function complies with the revision 1.0 of the PCI Power Management In- terface Specification. Description the function would normally as- sert the PME signal independent of the state of the PME_EN bit ...
Page 105
... RAP Register The RAP (Register Address Pointer) register is used to gain access to CSR and BCR registers on board the Am79C972 controller. The RAP contains the address of a CSR or BCR example of RAP use, consider a read access to CSR4. In order to access this register necessary ...
Page 106
... RDP access will depend upon the current setting of the RAP. RAP serves as a pointer into the CSR space. CSR0: Am79C972 Controller Status and Control Register Certain bits in CSR0 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ones to those bit locations ...
Page 107
... RXON is cleared by Am79C972 Initialization Done is set by the Am79C972 controller after the initialization sequence has com- pleted. When IDON is set, the Am79C972 controller has read the initialization block from mem- ory. When IDON is set, INTA is as- serted if IENA is 1 and the mask bit IDONM (CSR3, bit ...
Page 108
... Setting INIT clears the STOP bit. If STRT and INIT are set together, the Am79C972 controller initialization will be per- formed first. INIT is not cleared when the initialization sequence has completed. Read/Write accessible always. ...
Page 109
... The upper 8 bits that exist in the descriptor ad- dress registers and the buffer ad- dress registers which are stored on board the Am79C972 control- ler will be overwritten with the IADR[31:24] value, so that CSR accesses to these registers will show the 32-bit address that in- cludes the appended field ...
Page 110
... Am79C972 controller will scan through the next descriptor entries to locate the next STP bit that is set The Am79C972 controller will begin writing the next packets data to the buffer pointed to by that descriptor. Note that because several de- ...
Page 111
... BSWP is set big Endian mode is selected. When BSWP is set to 0, little Endian mode is se- lected. When big Endian mode is select- ed, the Am79C972 controller will swap the order of bytes on the AD bus during a data phase on ac- cesses to the FIFOs only. Specif- ically, AD[31:24] becomes Byte ...
Page 112
... H_RESET or S_RESET and is unaffected by the STOP bit. Missed Frame Counter Overflow is set by the Am79C972 control- ler when the Missed Frame Counter (CSR112 and CSR114) has wrapped around. When MFCO is set, INTA is as- serted if IENA is 1 and the mask bit MFCOM is 0. ...
Page 113
... UINT H_RESET or S_RESET or by setting the STOP bit. 5 RCVCCO Receive Collision Counter Over- flow is set by the Am79C972 con- troller when the Receive Collision Counter (CSR114 and CSR115) has wrapped around. When RCVCCO is set, INTA is asserted if IENA is 1 and the mask bit RCVCCOM is 0. ...
Page 114
... S_RESET or setting the STOP bit. Magic Packet Physical Logical Broadcast Accept. If MPPLBA is at its default value of 0, the Am79C972 controller will only de- tect a Magic Packet frame if the destination address of the packet matches the content of the physi- cal address register (PADR). If MPPLBA is set to 1, the destina- ...
Page 115
... Detailed Func- tions, Buffer Management Unit for details. In suspend mode, all of the CSR and BCR registers are accessi- ble. As long as the Am79C972 controller is not reset while in suspend mode (by H_RESET, S_RESET or by setting the STOP bit), no re-initialization of the de- vice is required after the device comes out of suspend mode ...
Page 116
... FIFOs or the SRAM. When FASTSPNDE is 0 and the SPND bit is set, the Am79C972 controller may take longer before entering the suspend mode. At the time the SPND bit is set, the Am79C972 controller will com- plete the DMA process of a trans- ...
Page 117
... Read/Write accessible always. STINTE is set H_RESET and is not affected by S_RESET or setting the STOP bit MII Management Read Error In- terrupt. The MII Read Error inter- rupt is set by the Am79C972 controller to indicate that the cur- rently read register from the ex- ternal PHY is invalid ...
Page 118
... S_RESET or setting the STOP bit 5 MCCINT MII Management Complete Interrupt. The MII Man- agement Command Complete In- terrupt is set by the Am79C972 controller when a read or write operation to the MII Data Port (BCR34) is complete. When MCCINT is set to 1, INTA is asserted if the enable bit MC- CINTE is set to 1. ...
Page 119
... S_RESET or setting the STOP bit. 1 MIIPDTINT MII PHY Detect Transition Inter- rupt. The MII PHY Detect Transi- tion Interrupt is set by the Am79C972 controller whenever the MIIPD bit (BCR32, bit 14) transitions from vice ver- sa. Read/Write accessible always. MIIPDTINT is cleared by the host by writing a 1 ...
Page 120
... Name Register, 31-16 RES 15-0 PADR[47:32]Physical read command CSR15: Mode This register’s fields are loaded during the Am79C972 controller initialization routine with the corresponding Initialization Block values, or when a direct register write has been performed on this register. Register, Bit Name 31-16 RES read ...
Page 121
... FCOLL 3 DXMTFCS Disable Transmit CRC (FCS). Am79C972 Disable Retry. When DRTY is set to 1, the Am79C972 controller will attempt only one transmission. In this mode, the device will not pro- tect the first 64 bytes of frame data in the Transmit FIFO from being overwritten, because auto- matic retransmission will not be necessary ...
Page 122
... Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. Description Reserved locations. Written as zeros and read as undefined. Contains the upper 16 bits of the current receive buffer address at which the Am79C972 controller will store incoming frame data. ...
Page 123
... Reserved locations. Written as zeros and read as undefined. 15-0 CXBAL Contains the lower 16 bits of the current transmit buffer address from which the Am79C972 con- troller is transmitting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...
Page 124
... STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR33: Next Transmit Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NXDAU Contains the upper 16 bits of the next transmit descriptor address pointer. Am79C972 ...
Page 125
... Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NNXDAU Contains the upper 16 bits of the next next transmit descriptor ad- dress pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. Am79C972 125 ...
Page 126
... RES Reserved locations. Written as zeros and read as undefined. 15-0 NRST Next Receive Status. This field is a copy of bits 31-16 of RMD1 of the next receive descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. Am79C972 ...
Page 127
... STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. Description Reserved locations. Written as zeros and read as undefined. ister contains the time that the Am79C972 controller will wait be- tween successive polling opera- tions. The RXPOLLINT value is expressed as the two’s comple- 127 ...
Page 128
... Note that since the advanced parity er- ror handling uses an additional bit in the descriptor, SWSTYLE (bits 7-0 of this register) must be set program the Am79C972 controller to use 32-bit software structures. APERREN does not affect the re- porting of address parity errors or ...
Page 129
... If SSIZE32 is set, then the soft- ware structures that are common to the Am79C972 controller and the host system will supply a full 32 bits for each address pointer that is needed by the Am79C972 controller for performing master accesses. The value of the SSIZE32 bit has no effect on the drive of the upper 8 address bits ...
Page 130
... Reserved locations. Written as zeros and read as undefined. 15-0 PXDAU Contains the upper 16 bits of the previous transmit descriptor ad- dress pointer. The Am79C972 controller has the capability to stack multiple transmit frames. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...