AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 20

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

PERR
Parity Error
During any slave write transaction and any master read
transaction, the Am79C971 controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C971 controller monitors PERR to see if the
target reports a data parity error.
When RST is active, PERR is an input for NAND tree
testing.
REQ
Bus Request
The Am79C971 controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the Am79C971 controller does not request
the bus. During Magic Packet mode, the REQ pin will
not be driven.
When RST is active, REQ is an input for NAND tree
testing.
RST
Reset
Input
When RST is asserted low, then the Am79C971 con-
troller performs an internal system reset of the type
H_RESET (HARDWARE_RESET, see section on RE-
SET). RST must be held for a minimum of 30 clock pe-
riods. While in the H_RESET state, the Am79C971
controller will disable or deassert all outputs. RST may
be asynchronous to clock when asserted or deas-
serted.
When RST is active, NAND tree testing is enabled.
SERR
System Error
During any slave transaction, the Am79C971 controller
asserts SERR when it detects an address parity error,
and reporting of the error is enabled by setting PER-
REN (PCI Command register, bit 6) and SERREN (PCI
Command register, bit 8) to 1.
By default SERR is an open-drain output. For compo-
nent test, it can be programmed to be an active-high
totem-pole output.
When RST is active, SERR is an input for NAND tree
testing.
STOP
Stop
In slave mode, the Am79C971 controller drives the
STOP signal to inform the bus master to stop the cur-
rent transaction. In bus master mode, the Am79C971
20
Input/Output
Input/Output
Input/Output
Input/Output
Am79C971
controller checks STOP to determine if the target wants
to disconnect the current transaction.
When RST is active, STOP is an input for NAND tree
testing.
TRDY
Target Ready
TRDY indicates the ability of the target of the transac-
tion to complete the current data phase. Wait states are
inserted until both IRDY and TRDY are asserted simul-
taneously. A data phase is completed on any clock
when both IRDY and TRDY are asserted.
When the Am79C971 controller is a bus master, it
checks TRDY during all read data phases to determine
if valid data is present on AD[31:0]. During all write data
phases, the device checks TRDY to determine if the
target is ready to accept the data.
When the Am79C971 controller is the target of a trans-
action, it asserts TRDY during all read data phases to
indicate that valid data is present on AD[31:0]. During
all write data phases, the device asserts TRDY to indi-
cate that it is ready to accept the data.
When RST is active, TRDY is an input for NAND tree
testing.
Board Interface
Note: Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12 first.
LED0
LED0
This output is designed to directly drive an LED. By de-
fault, LED0 indicates an active link connection on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The LED0
pin polarity is programmable, but by default it is active
LOW. When the LED0 pin polarity is programmed to
active LOW, the output is an open drain driver. When
the LED0 pin polarity is programmed to active HIGH,
the output is a totem pole driver.
Note: The LED0 pin is multiplexed with the EEDI pin.
When RST is active, LED0 is an input for NAND tree
testing.
LED1
LED1
This output is designed to directly drive an LED. By de-
fault, LED1 indicates receive activity on the network.
This pin can also be programmed to indicate other net-
work status (see BCR5). The LED1 pin polarity is pro-
grammable, but by default, it is active LOW. When the
LED1 pin polarity is programmed to active LOW, the
output is an open drain driver. When the LED1 pin po-
Input/Output
Output
Output