AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 124

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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SLPINT
SLPINTE
EXDINT
EXDINTE
Am79C971 controller when it
comes out of sleep mode.
When SLPINT is set, INTA is as-
serted if the enable bit SLPINTE
is 1. Note that the assertion of an
interrupt due to SLPINT is not de-
pendent on the state of the INEA
bit, since INEA is cleared by the
S_RESET reset generated when
entering the sleep mode.
Read/Write accessible always.
SLPINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. SLPINT
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
SLPINTE is set, the SLPINT bit
will be able to set the INTR bit.
Read/Write accessible always.
SLPINTE is set to 0 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
set by the Am79C971 controller
when the transmitter has experi-
enced Excessive Deferral on a
transmit frame, where Excessive
Deferral is defined in the ISO
8802-3 (IEEE/ANSI 802.3) stan-
dard.
When EXDINT is set, INTA is as-
serted if the enable bit EXDINTE
is 1.
Read/Write accessible always.
EXDINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. EXDINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
able. If EXDINTE is set, the
EXDINT bit will be able to set the
INTR bit.
Read/Write accessible always.
EXDINTE
H_RESET and is not affected by
Sleep Interrupt is set by the
Sleep
Excessive Deferral Interrupt is
Excessive Deferral Interrupt En-
Interrupt
is
set
is
Enable.
cleared
to
0
Am79C971
by
by
If
5
4
3
MPPLBA
MPINT
MPINTE
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MPPLBA is set to 0 by H_RESET
or S_RESET and is not affected
by setting the STOP bit.
Read/Write accessible always.
MPINT is cleared by the host by
writing a 1. Writing a 0 has no af-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
MPINT is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
Broadcast Accept. If MPPLBA is
at its default value of 0, the
Am79C971 controller will only de-
tect a Magic Packet frame if the
destination address of the packet
matches the content of the physi-
cal address register (PADR). If
MPPLBA is set to 1, the destina-
tion address of the Magic Packet
frame can be unicast, multicast,
or broadcast. Note that the set-
ting of MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame’s data sequence must be
made up of 16 consecutive phys-
ical addresses (PADR[47:0]) re-
gardless
destination address it has.
Magic Packet Interrupt. Magic
Packet Interrupt is set by the
Am79C971 controller when the
device is in the Magic Packet
mode and the Am79C971 con-
troller receives a Magic Packet
frame. When MPINT is set to 1,
INTA is asserted if IENA (CSR0,
bit 6) and the enable bit MPINTE
are set to 1.
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
Magic Packet Physical Logical
Magic Packet Interrupt Enable. If
MPINT
of
what
is
cleared
kind
by
of