AM7968-125DKC Advanced Micro Devices, AM7968-125DKC Datasheet - Page 93

• Manufacturer Part Number: AM7968-125DKC
• Description: TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
• Manufacturer: Advanced Micro Devices

Figure 8-2
8.2 Receiver Connections
Refer to Figure 8-2.
Grounding SERIN– puts the Receiver in Test Mode. SERIN+ is a single ended 100K
ECL NRZ input.
The X1 pin now becomes the bit rate clock input (bitclk), just like the CLK pin on the
Transmitter.
The CLK pin remains a byte rate CLK out.
8.3 Timing Relationships in Test Mode
The timing parameters in Test Mode are similar to the parameters in standard mode.
Propagation delay values remain the same, however bit time relationships are now
calculated with respect to the new bit times. For example, using a bitclk = 1.0 kHz, which
is a 1 ms period, the byte time t
the CLK falling to STRB rising delay is now [2 (t
Setup and Hold times for SERIN to X1 are not specified and must be determined for
each application.
Receiver Test Mode Connections
COMMAND OUT
DATA OUT
4, 3, 2
8, 9, 10
DATA STROBE
CMD STROBE
TAXIchip Integrated Circuits Technical Manual
DSTRB
CSTRB
VLTN
35
Am7969
Function
Function
= 10 bits x 1 ms = 10 ms. In the same way t
Normal
Normal
CNB
IGM
SERIN+
SERIN–
RESET
DMS
CLK
X1
X2
35
/n) + 15 ns] = 2.015 ms. Note that
DMS Can Be
Set For 8, 9, or
10-Bit Mode
Byte Rate CLK Out
Digital or Analog
Single Ended
Clock Recovery
Transmitter
Input From
Circuit
PLL
12330E-36
37
, which is
AMD
89