AK4525VF Asahi Kasei Microsystems, AK4525VF Datasheet - Page 9

• Manufacturer Part Number: AK4525VF
• Description: 20BIT STEREO ADC & DAC WITH X TAL OSC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n System Clock
The master clock (MCLK) can be a crystal resonator placed across the XTI and XTO pin. The relationship between the
MCLK and the desired sample rate is defined in Table 1. The MCLK frequency is set by CMODE pin and the sampling
rate corresponds to 32kHz
In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal
timing is synchronized to LRCK upon power-up. All external clocks must be present unless PDN= “L”, otherwise
excessive current may result from abnormal operation of internal dynamic logic.
When the state of CMODE changes under operation, the AK4525 should be reset by PDN. At that case, the analog
outputs should be muted externally because some click noise may occur.
External loading capacitor ( 22pF to AGND for XTI/XTO) are required for a crystal oscillator. PDN should be held “L”
for 5ms to allow the X’tal oscillation to begin at power-up.
MS0053-E-00
32.0kHz
44.1kHz
48.0kHz
fs
48kHz.
256fs
CMODE= “L”
11.2896MHz
12.2880MHz
8.1920MHz
Table 1. System Clock Example at normal speed
Figure 1. X’tal resonator connection
OPERATION OVERVIEW
384fs
CMODE= “H”
12.2880MHz
16.9344MHz
18.4320MHz
XTI
XTO
MCLK
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AK4525
512fs
CMODE= “NC”
16.3840MHz
22.5792MHz
24.5760MHz
2.8224MHz
3.0720MHz
2.0480MHz
SCLK
64fs
[AK4525]
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