AK4525VF Asahi Kasei Microsystems, AK4525VF Datasheet - Page 7

• Manufacturer Part Number: AK4525VF
• Description: 20BIT STEREO ADC & DAC WITH X TAL OSC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
(Ta=25 C; VA=4.5
Parameter
Master Clock Timing
MCKO Output
LRCK Timing
Serial Interface Timing
Reset Timing
Notes: 15. VD=3.1V, 0.8
MS0053-E-00
Rise Time
Fall time
256fs
384fs
512fs
Frequency
Duty Cycle
Frequency
Duty Cycle
Slave mode
Master mode
PDN Pulse Width
PDN “ ” to SDTO valid
SCLK Period
SCLK Pulse Width Low
LRCK Edge to SCLK “ ”
SCLK “ ” to LRCK Edge
LRCK to SDTO (MSB)
SCLK “ ” to SDTO
SDTI Hold Time
SDTI Setup Time
SCLK Frequency
SCLK Duty
SCLK “ ” to LRCK
SCLK “ ” to SDTO
SDTI Hold Time
SDTI Setup Time
16. SCLK rising edge must not occur at the same time as LRCK edge.
17. The AK4525 can be reset by bringing PDN “L”. When the state of CMODE changes during operation, the
18. These cycles are the number of LRCK rising from PDN rising.
AK4525 should be reset by PDN. PDN should be held “L” for 5ms to allow the X’tal oscillation to begin at
power-up.
Pulse Width High
5.5V; VD=3.1
2.0V.
(Note 18)
(Note 16)
(Note 16)
(Note 17)
(Note 15)
(Note 15)
SWITCHING CHARACTERISTICS
5.5V; C
L
=20pF)
Symbol
tMSLR
tSCKL
tSCKH
dMCK
fMCK
tLRM
dSCK
tSCK
tSDH
fSCK
tSDH
tPDV
tLRS
tSLR
tSSD
tSDS
tSSD
tSDS
tPD
dfs
tR
tF
fs
- 7 -
12.288
16.384
8.192
8.192
min
320
150
-20
32
45
65
65
45
45
40
25
40
25
64fs
516
typ
50
50
12.288
18.432
24.576
24.576
max
48
55
40
70
20
70
5
5
[AK4525]
Units
MHz
MHz
MHz
MHz
kHz
1/fs
2000/9
Hz
%
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns