AK4525VF Asahi Kasei Microsystems, AK4525VF Datasheet - Page 10

• Manufacturer Part Number: AK4525VF
• Description: 20BIT STEREO ADC & DAC WITH X TAL OSC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The AK4525 supports the master mode. In
this case, SCLK and LRCK are outputs and the frequency of SCLK is fixed to 64fs. Four serial data modes selected by the
DIF0 and DIF1 pins are supported as shown in Table 3. In all modes the serial data has MSB first, 2’s compliment format.
The data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the
least significant bits will be truncated.
MS0053-E-00
SCLK(i:32fs)
SDTO(o)
SDTI(i)
SCLK(i:64fs)
SDTO(o)
SDTI(i)
LRCK(i)
SCLK(i:64fs)
SDTO(o)
SDTI(i)
LRCK(i)
Mode
0
1
2
3
Note: In master mode, SCLK frequency is fixed to 64fs.
DIF1
0
0
1
1
0
0
0
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
19:MSB, 0:LSB
19
15 14 13
19
19
Don’t Care
Don’t Care
1
1
1
18
18
18
2
2
2
17
17
DIF0
3
3
0
1
0
1
8
12
15
11 10
19
7
3
7
17
13
Lch Data
Lch Data
9
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS (I2S)
14
18
2
6
6
10
18
14
13
SDTO (ADC)
9
5
1
11
19
Table 2. Serial Data Modes
12 11
12 11
0
0
4
Figure 2. Mode 0 Timing
Figure 3. Mode 1 Timing
8
12
20
20
7
3
13
21
2
6
2
14
30
- 10 -
1
1
1
5
15
31
31
4
0
0
0
16bit, LSB justified
20bit, LSB justified
20bit, MSB justified
IIS (I2S)
0
0
0
19 18
15
19 18
19 18
Don’t Care
Don’t Care
SDTI (DAC)
1
1
1
14 13
2
2
2
17
17
3
8
12
15
19
11 10
7
7
3
13
Rch Data
17
Rch Data
9
14
18
6
2
6
10
18
14
13
5
1
9
L/R
H/L
H/L
L/H
H/L
19
11
12 11
12 11
4
0
0
8
12
20
20
7
3
13
21
SCLK (Slave)
6
2
2
32fs or
14
5
1
1
1
15
31
31
32fs
40fs
40fs
[AK4525]
4
0
0
0
40fs
0
0
0
2000/9
19
15
19
19
1
1
1