ISPLSI5256VA-125LB208 Lattice Semiconductor, ISPLSI5256VA-125LB208 Datasheet - Page 16

• Manufacturer Part Number: ISPLSI5256VA-125LB208
• Description: In-System Programmable 3.3V SuperWIDE High Density PLD
• Manufacturer: Lattice Semiconductor

Power consumption in the ispLSI 5256VA device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of four product terms
has a single speed/power tradeoff control fuse that acts
Figure 10. Typical Device Power Consumption vs fmax
I CC can be estimated for the ispLSI 5256VA using the following equation:
High Speed Mode: ICC = 30 + (# of PTs * 0.456) + (# of nets * Max. freq * 0.0039)
Low Power Mode: ICC = 30 + (# of PTs * 0.22) + (# of nets * Max. freq * 0.0039)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I CC estimate is based on typical conditions (V CC = 3.3V, room temperature) and an assumption of 2 GLB loads
on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions
and the program in the device, the actual I CC should be verified.
Power Consumption
400
350
300
250
200
150
100
0
Notes: Configuration of 16 16-bit Counters
20
Typical Current at 3.3V, 25 C
40
f
max (MHz)
60
ispLSI 5256VA
High Speed Mode
16
on the complete group of four. The fast “high-speed”
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “low-
power” setting will significantly reduce the power
dissipation for these product terms. Figure 10 shows the
relationship between power and operating speed.
80
Specifications ispLSI 5256VA
ispLSI 5256VA
Low Power Mode
100
120
140
0127/5256va