GAL22V10 Lattice Semiconductor, GAL22V10 Datasheet - Page 17

• Manufacturer Part Number: GAL22V10
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1 s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
Power-Up Reset
Input/Output Equivalent Schematics
(Vref Typical = 3.2V)
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
INTERNAL REGISTER
Typical Input
OUTPUT REGISTER
OUTPUT REGISTER
Vcc
Active Pull-up
Circuit
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
Vref
C L K
V c c
Vcc
Vcc (min.)
Vcc
t
17
pr
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
Data
Output
t
wl
Specifications GAL22V10
t
su
Tri-State
Control
Feedback
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
(Vref Typical = 3.2V)
PIN
PIN