GAL20V8Z-12QP Lattice Semiconductor, GAL20V8Z-12QP Datasheet - Page 15

• Manufacturer Part Number: GAL20V8Z-12QP
• Description: Zero Power E2CMOS PLD
• Manufacturer: Lattice Semiconductor

Output Load Conditions (see figure)
3-state levels are measured 0.5V from steady-state active
level.
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Specifications
Test Condition
A
B
C
Note: fmax with external feedback is calculated from
measured tsu and tco.
Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.
f
Active High
Active Low
Active High
Active Low
max with External Feedback 1/(
L O G I C
A R R A Y
LOGIC
ARRAY
t
su +
t
f
s u
max with No Feedback
t
h
300
300
300
R
1
REGISTER
R EG I S T E R
C L K
CLK
390
390
390
390
390
R
3ns 10% – 90%
2
t
t
GND to 3.0V
c o
su+
See Figure
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
15
FROM OUTPUT (O/Q)
UNDER TEST
*C
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
L
Specifications GAL20V8Z
f
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
max with Internal Feedback 1/(
LOGIC
ARRAY
R
2
+5V
t
cf
t
pd
REGISTER
GAL20V8ZD
R
CLK
1
C *
t
su+
L
TEST POINT
t
cf)