GAL20V8Z LATTICE [Lattice Semiconductor], GAL20V8Z Datasheet
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GAL20V8Z
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GAL20V8Z Summary of contents
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... High Speed Graphics Processing • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL20V8Z and GAL20V8ZD, at 100 A standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad- ...
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... Tsu (ns) Tco (ns GAL20V8ZD: Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns Part Number Description Device Name GAL20V8Z (Zero Power ITD) GAL20V8ZD (Zero Power DPP) Speed (ns) Active Power Q = Quarter Power Icc (mA 100 GAL20V8Z-12QP 55 100 GAL20V8Z-12QJ 10 55 ...
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... When using the standard GAL20V8 JEDEC fuse pattern generated by the logic compilers for the GAL20V8ZD, special attention must be given to pin 4(5) (DPP) to make sure that it is not used as one of the functional inputs. ...
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... Specifications GAL20V8Z Registered outputs have eight product terms per output. I/Os have seven product terms per output. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page ...
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... PTD 2703 .... 2630, 2631 .... Byte1 Byte0 5 Specifications GAL20V8Z GAL20V8ZD 23(27) OLMC 22(26) XOR-2560 AC1-2632 OLMC 21(25) XOR-2561 AC1-2633 OLMC 20(24) XOR-2562 AC1-2634 OLMC 19(23) XOR-2563 AC1-2635 OLMC 18(21) XOR-2564 AC1-2636 OLMC 17(20) XOR-2565 AC1-2637 OLMC 16(19) XOR-2566 AC1-2638 OLMC 15(18) XOR-2567 AC1-2639 14(17) OE 13(16) SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD ...
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... All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1(2) and 13(16) are always available as data inputs into the AND array. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page ...
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... PTD 2703 .... 2630, 2631 .... Byte1 Byte0 7 GAL20V8ZD 23(27) OLMC 22(26) XOR-2560 AC1-2632 OLMC 21(25) XOR-2561 AC1-2633 OLMC 20(24) XOR-2562 AC1-2634 OLMC 19(23) XOR-2563 AC1-2635 OLMC 18(21) XOR-2564 AC1-2636 OLMC 17(20) XOR-2565 AC1-2637 OLMC 16(19) XOR-2566 AC1-2638 OLMC 15(18) XOR-2567 AC1-2639 14(17) 13(16) SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD ...
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... Pins 1(2) and 13(16) are always available as data inputs into the AND array. The center two macrocells (pins 18(21) & 19(23)) can- not be used in the input configuration. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram ...
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... Byte1 Byte0 9 GAL20V8ZD 2640 PTD 23(27) OLMC XOR-2560 22(26) AC1-2632 OLMC XOR-2561 21(25) AC1-2633 OLMC XOR-2562 20(24) AC1-2634 OLMC XOR-2563 19(23) AC1-2635 OLMC XOR-2564 18(21) AC1-2636 OLMC XOR-2565 17(20) AC1-2637 OLMC XOR-2566 16(19) AC1-2638 OLMC XOR-2567 15(18) AC1-2639 14(17) 13(16) 2703 SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD ...
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... -100 A Vin = 0.5V CC OUT = GND V = Vcc Outputs Open 0. 3. MHz Outputs Open = MAXIMUM Specifications GAL20V8Z GAL20V8ZD ) ............................... MIN. TYP. 2 — Vss – 0.5 2.0 — — — — — — — 2.4 — ...
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... Add sa to pd, su, en and dis when the device is coming out of standby state. Standby Power Timing Waveforms Icc POWER Isb INPUT or I/O FEEDBACK OE CLK OUTPUT Specifications GAL20V8Z Specifications GAL20V8Z Over Recommended Operating Conditions en GAL20V8ZD COM ...
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... OE to Output Enabled t dis C Input or I/O to Output Disabled Output Disabled 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Specifications GAL20V8Z Specifications GAL20V8ZD Over Recommended Operating Conditions 12 GAL20V8ZD COM COM -12 -15 UNITS MIN ...
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... DPP Low to Valid Clock t dlov A DPP Low to Valid Output 1) Refer to Switching Test Conditions section. Dedicated Power-Down Pin Timing Waveforms DPP INPUT or I/O FEEDBACK OE CLK OUTPUT Specifications GAL20V8Z Specifications GAL20V8ZD Over Recommended Operating Conditions t t ivdh dhix t t gvdh dhgx t t cvdh ...
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... CLK f 1/ max (w/o fb) Clock Width INPUT or I/O FEEDBACK t pd CLK REGISTERED OUTPUT REGISTERED OUTPUT t wl CLK REGISTERED FEEDBACK 14 Specifications GAL20V8Z GAL20V8ZD VALID INPUT max (external fdbk) Registered Output t t dis Output Enable/Disable f 1/ max (internal fdbk ...
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... See Figure FROM OUTPUT (O/Q) UNDER TEST 390 50pF 390 50pF 390 50pF 390 5pF *C 390 5pF 15 Specifications GAL20V8Z GAL20V8ZD CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ + INCLUDES TEST FIXTURE AND PROBE CAPACITANCE ...
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... Dedicated Power-Down Pin The GAL20V8ZD uses pin 4 (pin 5 on PLCC) as the dedicated power-down signal to put the device in power-down state. DPP is an active high signal where logic high driven on this signal puts the device into power-down state ...
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... Vcc CLK t pr asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL20V8Z/ZD. First, the V pr MAX result, must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of normal system operation, avoid clocking the device until all input and feedback path setup times have been met ...
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... RISE -1.5 FALL - Number of Outputs Switching Delta Tco vs Output Loading 10 RISE 8 FALL 100 150 200 250 300 Specifications GAL20V8Z GAL20V8ZD Normalized Tsu vs Vcc 1.4 RISE 1.3 FALL 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.50 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 Temperature (deg. C) Switching RISE ...
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... Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 5.50 -55 - Temperature (deg. C) Input Clamp (Vik -1.00 -0.80 -0.60 -0.40 -0.20 Vik (V) 19 Specifications GAL20V8Z GAL20V8ZD Voh vs Ioh 5 4.5 4 3.5 3 2.5 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. (DPP & ITD > 10MHz) 1.30 1.20 1.10 1.00 0.90 0.80 100 125 Frequency (MHz) Normalized Icc vs Freq. (ITD) 1 0.8 0.6 0.4 ...