ispPAC10-01PI Lattice Semiconductor, ispPAC10-01PI Datasheet - Page 17

• Manufacturer Part Number: ispPAC10-01PI
• Description: In-System Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor

Design Simulation Capability
A powerful feature of PAC-Designer is its simulation
capability enabling quick and accurate verification of
circuit operation and performance. Once a circuit is
configured via the interactive design process, gain and
phase response between any input and output can then
be determined. This function is part of the simulator
capability which derives a transfer equation between the
two points and then sweeps it over the user-specified
frequency range. Figure 13 shows a typical screen plot of
the gain/phase simulator. In it are the input to output
response curves of a 2nd order biquad filter similar to the
implementation illustrated in Figure 7b. In this example,
the lowpass and bandpass characteristics of the filter are
seen.
The simulator is capable of displaying up to four separate
input to output responses. This allows multiple signal
paths to be viewed as well as intermediate results of
component changes so performance comparisons can
be made. There is also a user positioned crosshair cursor
Figure 13. PAC-Designer Simulation Plot Screen (Biquad Filter Configuration)
Software-Based Design Environment (Continued)
Ready
Gain Plot (dB)
Phase Plot (Deg)
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PAC Designer - [Design1:2]
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Tools
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Window
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that intersects the curves on the plot, and reads out the
gain and frequency in the lower right hand corner of the
plot window when activated.
In-System Programming
The ispPAC10 is an in-system programmable device.
This is accomplished by integrating all high voltage
programming circuitry on-chip. Programming is performed
through a 5-wire, IEEE 1149.1 (JTAG) compliant serial
port interface at normal logic levels. Once a device is
programmed, all configuration information is stored in on-
chip, non-volatile E
of the IEEE 1149.1 serial interface are described in the
interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in
the E
be configured by the user to store unique data such as ID
codes, revision numbers or inventory control data.
Help
Curve:1 Vout1/Vin1
2
100K
100K
memory of the ispPAC10. It contains 8 bits that can
Specifications ispPAC10
1M
1M
2
CMOS memory cells. The specifics
10M
10M
Vo1/Vi1
Vo2/Vi1
Vo1/Vi1
Vo2/Vi1