AK5356VN Asahi Kasei Microsystems, AK5356VN Datasheet - Page 19

• Manufacturer Part Number: AK5356VN
• Description: LOW POWER 20BIT ADC WITH MIC AMP & PGA
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
Input Analog PGA Control
[ Writing to IPGA register at ZEIP = “1” continuously ]
MS0171-E-00
Addr
03H
When writing control register continuously, the change of IPGA should be written after zero crossing timeout. If
IPGA is changed by writing to control register before zero crossing detection, IPGA value of L/R channels may not
give a difference level.
ZEIP:
IPGA6-0: Input Analog PGA, 97 levels; 00H=MUTE
Register Name
Input Analog PGA Control
Default
Select IPGA zero crossing operation
In the timeout cycle, it is possible to set in ZTM1-0 bit. When ZTM1-0 is “11”, timeout cycle is
2048/fs = 46.4ms (@fs=44.kHz). When ZEIP is “0”, IPGA changes immediately.
0: Disable (Default)
1: Enable
Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by zero crossing detection
or timeout independently.
ON/OFF of zero crossing detection can be controlled by ZEIP bit.
DATA
5EH
0EH
60H
5FH
28H
27H
19H
18H
17H
16H
11H
10H
0FH
05H
04H
03H
02H
01H
00H
ZEIP
D7
0
Table 4. Input Gain Setting
GAIN(dB)
IPGA6
MUTE
D6
+28.0
+27.5
+27.0
-10.0
-15.0
-16.0
-18.0
-20.0
-38.0
-40.0
-44.0
-48.0
-52.0
+0.0
-0.5
-7.5
-8.0
-9.0
- 19 -
IPGA5
D5
0.5dB
Step
1dB
2dB
4dB
IPGA4
D4
Level
73
12
IPGA3
8
3
1
28H
D3
IPGA2
D2
IPGA1
D1
[AK5356]
2002/08
IPGA0
D0