AK5356VN Asahi Kasei Microsystems, AK5356VN Datasheet - Page 15

• Manufacturer Part Number: AK5356VN
• Description: LOW POWER 20BIT ADC WITH MIC AMP & PGA
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n System Reset
The AK5356 is placed in the power-down mode by bringing PDN pin “L”. The control registers are also reset at the same
time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down
mode. The output data SDTO becomes available after 4128 cycles of LRCK clocks. During initialization, the ADC digital
data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the
input signal at the end of initialization (Settling time equals the group delay time approximately.).
As a normal initialization cycle may not be executed, nothing writes at address 01H during
initialization cycle after exiting power-down by PDN pin.
Power Supply
ADC Internal
Control register
W rite to register
MS0171-E-00
PDN pin
External clocks
AIN
SDTO
State
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to the analog input is delayed by the Group Delay amount (GD). Output signal
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of
(3). ADC output data is “0” at power-down.
(4). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5356 should be placed in the
(5). When external clocks are not supplied, inhibits writing to all control registes.
PD:
PM:
INIT-1:
INIT-2:
Inhibit:
gradually comes to settle to input signal during a group delay.
a internal.
power-down state.
PDN pin may be “L” at power-up.
Power-down state. ADC is output “0”.
Power-down state by Power Management bit. ADC is output “0”.
Initialization cycle of ADC
Initializing all control registers.
Inhibits writing to all control registers.
Inhibit
INIT -2
PD
Figure 10. Power-Up / Power-Down Timing Example
(4)
INIT -1
GD
4128/fs
“0”data
The clocks m ay be stopped.
- 15 -
Normal
Normal
Idle Noise
Normal
GD (1)
(2)
(3) “0”data
PM
(5)
INIT -1
4128/fs
Normal
[AK5356]
(1)
2002/08
GD