AK5356VN Asahi Kasei Microsystems, AK5356VN Datasheet - Page 12

• Manufacturer Part Number: AK5356VN
• Description: LOW POWER 20BIT ADC WITH MIC AMP & PGA
• Manufacturer: Asahi Kasei Microsystems

n System Clock
The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs, 40fs ). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The Frequency of MCLK can be
input at 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling
frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5356 may draw excess current and will not operate properly because it utilizes these clocks
for internal dynamic refresh of registers. If the external clocks are not present, the AK5356 should be placed in
power-down mode.
n Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes,
MSB-first and 2’s compliment. The data format is set using the DIF bit. SDTO is latched by a falling edge of BCLK.
MS0171-E-00
BCLK(i:32fs)
LRCK
BCLK(I:64fs)
SDTO(o)
SDTO (o)
No.
0
0
1
0
19
19
19:MSB, 0:LSB
1
1
18
18
DIF bit
2
2
17
0
1
8
3
12
11
7
9
13
Lch Data
16bit I
20bit I
16bit MSB justified
20bit MSB justified
10
6
SDTO (ADC)
10
14
Figure 7. Audio Data Timing (No.0)
9
2
2
S compatible
S compatible
11
19
OPERATION OVERVIEW
Table 1. Audio Data Format
0
8
12
20
7
13
21
6
14
- 12 -
5
15
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
Lch: “L”, Rch: “H”
31
4
0
0
19
19 18
LRCK
1
1
18
2
2
17
3
8
3
12
11
7
BCLK
= 32fs
= 32fs
13
Rch Data
9
10
40fs
40fs
6
14
10
9
19
11
8
0
Default
20
12
7
21
13
6
14
5
31
15
4
2002/08
0
0
19
19
1
1