COP87L89RB National Semiconductor, COP87L89RB Datasheet - Page 62

• Manufacturer Part Number: COP87L89RB
• Description: 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory/ CAN Interface/ 8-Bit A/D/ and USART
• Manufacturer: National Semiconductor

www.national.com
Memory Map
Address
00CB
00CC
00CD to
00CE
00CF
00D0
00D1
00D2
00D3
00D4
00D5
00D6
00D7
00D8
00D9
00DA
00DB
00DC
00DD to
00DF
00E0 to
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
(Continued)
A/D Converter Control
Register (Reg:ENAD)
A/D Converter Result Register
(Reg:ADRSLT)
Reserved
IDLE Timer Control Register
(Reg:ITMR)
PORTLD, Port L Data
Register
PORTLC, Port L
Configuration Register
PORTLP, Port L Input Pins
(Read Only)
Reserved for Port L
PORTGD, Port G Data
Register
PORTGC, Port G
Configuration Register
PORTGP, Port G Input Pins
(Read Only)
Port I Input Pins (Read Only)
Port CD, Port C Data Register
Port CC, Port C Configuration
Register
Port CP, Port C Input Pins
(Read Only)
Reserved for Port C
Port D
Reserved for Port D
Reserved for EE Control
Registers
Timer T1 Autoload Register
T1RB Lower Byte (T1BRLO)
Timer T1 Autoload Register
T1RB Upper Byte (T1BRHI)
ICNTRL Register
MICROWIRE/PLUS Shift
Register (SOIR)
Timer T1 Lower Byte
(TMR1LO)
Timer T1 Upper Byte
(TMR1HI)
Timer T1 Autoload Register
T1RA Lower Byte (T1RALO)
Timer T1 Autoload Register
T1RA Upper Byte (T1RAHI)
CNTRL, Control Register
PSW, Processor Status Word
Register
Contents
62
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or
decrement of pointer)
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that au-
tomatically post increments or decrements the B or X regis-
ter after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the oper-
and.
Short Immediate
This addressing mode is used with the Load B Immediate in-
struction. The instruction contains a 4-bit immediate field as
the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new pro-
gram location. JP has a range from −31 to +32 to allow a
1-byte relatie jump (JP + 1 is implemented by a NOP instruc-
tion). There are no “pages” when using JP, since all 15 bits of
PC are used.
Address
00F0 to
00FB
00FC
00FD
00FE
00FF
0100 to 013F
Reading memory locations 0070H–007FH will
return all ones. Reading unused memory locations
00xxH–00xxH will return undefined data. Reading
memory locations from other Segments (i.e.
segment 2, segment 3, ...etc.) will return undefined
data.
On-Chip RAM Mapped as
Registers
X Register
SP Register
B Register
S Register
On-Chip RAM Bytes (64
Bytes)
Contents