COP87L89RB National Semiconductor, COP87L89RB Datasheet - Page 23

• Manufacturer Part Number: COP87L89RB
• Description: 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory/ CAN Interface/ 8-Bit A/D/ and USART
• Manufacturer: National Semiconductor

Functional Block Description of
the CAN Interface
The PS2..PS0 bits fix the number of Prescaler clock cycles
per bit time for phase segment 1 and phase segment 2. The
PS2..PS0 bits also set the synchronization Jump Width to a
value equal to the lesser of: 4 PSC, or the length of PS1/2
(Min: 4 l length of PS1/2).
Bits 1 and 0 are reserved and should be zero.
LENGTH OF TIME SEGMENTS (See Figure 28 )
Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from
CAN BUS CONTROL REGISTER (CBUS) (00AA)
Reserved These bits are reserved and should be zero.
RIAF
If the RIAF bit is set to zero, bits 4 to 10 of the received iden-
tifier are compared with the mask bits of RID4..RID10 and if
the corresponding bits match, the message is accepted. If
the RIAF bit is set to a one, the filter function is disabled and
all messages independent of the identifier will be accepted.
TxEN0, TxEN1 TxD Output Driver Enable
• The Synchronization Segment is 1 CAN Prescaler clock
• The Propagation Segment can be programmed (PPS) to
• Phase Segment 1 and Phase Segment 2 are program-
served
PS2
Bit 7
Re-
TxEN1
0
0
0
0
1
1
1
1
(PSC)
be 1,2...,8 PSC in length.
mable (PS) to be 1,2,..,8 PSC long.
the rx-pins through the receive comparator (worst case assumption: 3
clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set
the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-
munication on the bus under all circumstances. With prescaler settings
of 0 this is a given (i.e., no caution has to be applied).
Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example
for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz
CKI and CSCAL = 0.
0
0
1
RIAF
TABLE 5. Synchronization Jump Width
PS1
0
0
1
1
0
0
1
1
Receive identifier acceptance filter bit
TxEN1
TxEN0
TABLE 6. Output Drivers
PS0
0
1
0
0
1
0
1
0
1
0
1
TxEN0
Segment
Length of
Tx0, Tx1 TRI-STATE, CAN
input comparator disabled
Tx0 enabled
Tx1 enabled
Phase
1 t
2 t
3 t
4 t
5 t
6 t
7 t
8 t
RxREF1
can
can
can
can
can
can
can
can
(Continued)
1
⁄
2
RxREF0
Output
Synchronization
Jump Width
served
1 t
2 t
3 t
4 t
4 t
4 t
4 t
4 t
Re-
can
can
can
can
can
can
can
can
FMOD
Bit 0
23
Bus synchronization of the device is done in the following
way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either
TxEN1 or TxEN0, or both are set to 1, the device will not start
transmission or reception of a frame until eleven consecutive
“recessive” bits have been received. Resetting the TxEN1
and TxEN0 bits will disable the output drivers and the CAN
input comparator. All other CAN related registers and flags
will be unaffected. It is recommended that the user reset the
TxEN1 and TxEN0 bits before switching the device into the
HALT mode (the CAN receive wakeup will still work) in order
to reduce current consumption and to assure a proper resy-
chronization to the bus after exiting the HALT mode.
Note: A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE
RXREF1 Reference voltage applied to Rx1 if bit is set
RXREF0 Reference voltage applied to Rx0 if bit is set
FMOD
Setting the FMOD bit to “0” (default after power on reset) will
select the Standard Fault Confinement mode. In this mode
the device goes from “bus off” to “error active” after monitor-
ing 128*11 recessive bits (including bus idle) on the bus. This
mode has been implemented for compatibility with existing
solutions. Setting the FMOD bit to “1” will select the En-
hanced Fault Confinement mode. In this mode the device
goes from “bus off” to “error active” after monitoring 128
“good” messages, as indicated by the reception of 11 con-
secutive “recessive” bits including the End of Frame,
whereas the standard mode may time out after 128 x 11 re-
cessive bits (e.g., bus idle).
TRANSMIT CONTROL/STATUS (TCNTL) (00AB)
NS1..NS0 Node Status, i.e., Error Status.
The Node Status bits are read only.
TERR
This bit is automatically set when an error occurs during the
transmission of a frame. TERR can be programmed to gen-
erate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit must be cleared by the user’s software.
Note: This is used for messages for more than two bytes. If an error occurs
RERR Receiver Error
This bit is automatically set when an error occurred during
the reception of a frame. RERR can be programmed to gen-
NS1
Bit 7
TxEN1
(independent of the values of the TxEN1 and TxEN0 bits).
during the transmission of a frame with more than 2 data bytes, the us-
er’s software has to handle the correct reloading of the data bytes to
the TxD registers for retransmission of the frame. For frames with 2 or
fewer data bytes the interface logic of this chip does an automatic re-
transmission. Regardless of the number of data bytes, the user’s soft-
ware must reset this bit if CEIE is enabled. Otherwise a new interrupt
will be generated immediately after return from the interrupt service
routine.
1
NS1
0
0
1
1
NS0
Transmit Error
Fault Confinement Mode select
TxEN0
TERR
TABLE 7. Node Status
1
NS0
0
1
0
1
RERR
Tx0 and Tx1 enabled
CEIE
Error active
Error passive
Bus off
Bus off
Output
TIE
Output
RIE
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TXSS
Bit 0