MCF5232 ETC, MCF5232 Datasheet - Page 16

• Manufacturer Part Number: MCF5232
• Description: Integrated Microprocessor Hardware Specification
• Manufacturer: ETC

Modes of Operation
3.2
The following features are available to support applications which require low power.
There are four modes of operation: RUN, WAIT, DOZE, and STOP. The system enters a low power mode
when the user programs the low power bits (LPMD) in the LPCR (Low Power Control Register) in the
CIM before the CPU core executes a STOP instruction. This idles the CPU with no cycles active. The
LPMD bits indicate to the system and clock controller to power down and stop the clocks appropriately.
During STOP mode, the system clock is stopped low.
A wakeup event is required to exit a low power mode and return back to RUN mode. Wakeup events
consist of any of the following conditions. See the following sections for more details.
3.2.1
RUN mode is the normal system operating mode. Current consumption in this mode is related directly to
the frequency chosen for the system clock.
16
•
•
•
1. Any type of reset.
2. Assertion of the BKPT pin to request entry into Debug mode.
3. Debug request bit in the BDM control register to request entry into debug mode.
4. Any valid interrupt request.
D25, D24
JTAG_EN
Four modes of operation:
— RUN
— WAIT
— DOZE
— STOP
Ability to shut down most peripherals independently.
Ability to shut down the external CLKOUT pin.
Low Power Modes
RUN Mode
Pin
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Select chip select /
address line
Selects BDM or
JTAG mode
Chip Configuration
Table 3. Configuration Pin Descriptions (continued)
Function
00 PADDR[7:5] configured
10 PADDR7 configured as
01 PADDR[7:6] configured
11 PADDR[7:5] configured
0 BDM mode
1 JTAG mode
Preliminary
as A23-A21 (default)
CS6,
PADDR[6:5] as A22-A21
as CS[6:5],
PADDR5 as A21
as CS[6:4]
Pin State/Meaning
Comments
Freescale Semiconductor