P80C557E4 Philips Semiconductors, P80C557E4 Datasheet - Page 44

• Manufacturer Part Number: P80C557E4
• Description: Single-chip 8-bit microcontroller
• Manufacturer: Philips Semiconductors

Philips Semiconductors
6.13 32kHz PLL Oscillator with Seconds Timer
6.13.1 XTAL3,4 Oscillator Circuitry
The input signal SELXTAL1 connected to logic “0” selects the 32kHz
oscillator together with the PLL instead of the XTAL1,2 oscillator,
which is halted. XTAL2 is floating in that case.
The 32kHz oscillator consists of an inverter, which forms a Pierce
oscillator with the on-chip components C1,C2,Rf and an external
crystal of 32768 Hz.
During the following situations, the inverter is switched to tristate and
XTAL3 is pulled to Vss :
6.13.2 PLL CCO
A current controlled oscillator (CCO) generates a clock frequency
f
the 32kHz oscillator as the reference clock. The system clock
frequency f
contents of the PLL control register (PLLCON):
f
Table 41). The maximum locking time is 10 ms
During the stabilization phase, no time critical routines should be
executed.
Table 41. PLLCON
1999 Mar 02
CCO
CCO
NOTE:
1. This parameter is characterized.
RUN32
ENSECI
SECINT
FSEL.4
to
FSEL.0
during Power-down Mode, when the PLL control register bit
RUN32 (PLLCON.7) was set to ’0’;
during Reset (RSTIN = HIGH) ;
when the XTAL1,2 oscillator is selected (SELXTAL1 = HIGH).
Single-chip 8-bit microcontroller
Other combinations, than mentioned above, are reserved and may not be selected. This allows to generate the standard baudrates 19200,
9600, 4800, 2400 and 1200 Baud, when using the UART and Timer1.
SYMBOL
of approx. 32 , 38 , 44 or 50 MHz , controlled by the PLL, with
can be changed via the PLLCON bits FSEL(1:0) (see
PLLCON (F9H)
CLK
can be varied under software control by changing the
PLLCON.7
PLLCON.6
PLLCON.5
PLLCON.4
to
PLLCON.0
BIT
RUN32
RUN32 = 0: The 32 kHz oscillator halts during Power-down.
RUN32 = 1: The 32 kHz oscillator stays running during Power-down.
Enable the seconds interrupt. (enabling INT1 is also required)
Seconds interrupt requested by an overflow of the seconds timer (which occurs every second) or via writing
a ‘1’ to this bit. SECINT can only be cleared by writing a ’0’ to this bit .
System clock frequency in MHz
7
FSEL[1:0]
ENSECI
1
.
6
Figure 44. PLL control register (PLLCON).
11
10
01
00
SECINT
5
100
3.93
4.72
5.51
6.29
44
FSEL.4
4
P83C557E4/P80C557E4/P89C557E4
The system clock frequency f
of the PLLCON bits FSEL(4:0) (see Table 41).
If only FSEL(4:2) is changed but not FSEL(1:0), then it takes about
1us until the new frequency is available.
Changing the system clock frequency has to be done in two steps.
From HIGH to LOW frequencies:
First change (FSEL(4:2), then FSEL (1:0).
From LOW to HIGH frequencies:
First change only FSEL (1:0) and after a stabilization phase of
10 ms change FSEL (4:2).
6.13.3 PLL Control Register – PLLCON
PLLCON is a special function register, which can be read and
written by software. It contains the control bits:
PLLCON is initialized to 0DH upon Reset (RSTIN = ‘1’) or Watchdog
Timer Overflow. PLLCON = 0DH corresponds to a system clock
frequency of 11.01 MHz.
to select one of several system clock frequencies (see Table 41);
the seconds interrupt flag: SECINT
to enable the seconds interrupt flag: ENSECI
the RUN32 bit, which defines if during Power-down Mode the
32kHz oscillator is halted or stays running.
FUNCTION
FSEL[4:2]
FSEL.3
12.58
11.01
7.86
9.44
3
011
FSEL.2
2
15.73
CLK
010
is derived from f
FSEL.1
1
Product specification
CCO
FSEL.0
0
under control