LH28F004SU-LC Sharp Electrionic Components, LH28F004SU-LC Datasheet - Page 5

• Manufacturer Part Number: LH28F004SU-LC
• Description: 4M (512K bb 8) Flash Memory
• Manufacturer: Sharp Electrionic Components

4M (512K × 8) Flash Memory
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP
locked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory’s Status Register. This
register, when used alone, provides a straightforward
upgrade capability to the LH28F004SU-LC from a
LH28F008SA-based design.
RY
tie many RY
figuration such as a Resident Flash Array.
access time of 120 ns (t
3.6 V) over the commercial temperature range (0 to
+70°C). A corresponding maximum access time of
160 ns (t
reduced power consumption applications.
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
when the RP
transitions low, any current operation is aborted and the
device is put into the deep power down mode. This mode
brings the device power consumption to less than 5 µA,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on. RP
return the device to default configuration. When the
power transition is occurred, or at the power on/off, RP
is required to stay low in order to protect data from noise.
A recovery time of 620 ns is required from RP
ing high until outputs are again valid. In the Deep Power-
Down state, the WSM is reset (any current operations
will abort) and the CSR register is cleared.
CE
control pins a CMOS levels. In this mode, the device
draws an I
When the device power-up or RP
The LH28F004SU-LC contains a Compatible Status
The LH28F004SU-LC incorporates an open drain
The LH28F004SU-LC is specified for a maximum
The LH28F004SU-LC incorporates an Automatic
In APS mode, the typical I
A Deep Power-Down mode of operation is invoked
A CMOS Standby mode of operation is enabled when
»
»
/ BY
transitions high and RP
»
output pin. This feature allows the user to OR-
ACC
CC
»
/ BY
) at 2.7 V (0 to +70°C) is achieved for
»
standby current of 8 µA.
(called PWD on the LH28F008SA) pin
»
pins together in a multiple memory con-
»
ACC
pin is turned to low in order to
»
) at 3.3 V operation (3.0 to
CC
turns High, Erase All Un-
»
stays high with all input
current is 1 mA at 3.3 V.
»
turns High, Write
»
switch-
»
MEMORY MAP
7BFFFH
6BFFFH
5BFFFH
4BFFFH
3BFFFH
2BFFFH
1BFFFH
0BFFFH
7FFFFH
7C000H
77FFFH
73FFFH
6FFFFH
6C000H
67FFFH
63FFFH
5FFFFH
5C000H
57FFFH
53FFFH
4FFFFH
4C000H
47FFFH
43FFFH
3FFFFH
3C000H
37FFFH
33FFFH
2FFFFH
2C000H
27FFFH
23FFFH
1FFFFH
1C000H
17FFFH
13FFFH
0FFFFH
0C000H
07FFFH
03FFFH
78000H
74000H
70000H
68000H
64000H
60000H
58000H
54000H
50000H
48000H
44000H
40000H
38000H
34000H
30000H
28000H
24000H
20000H
18000H
14000H
10000H
08000H
04000H
00000H
Figure 3. Memory Map
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
LH28F004SU-LC
28F004SUT-LC12-3
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