M95010 ST Microelectronics, M95010 Datasheet - Page 8

• Manufacturer Part Number: M95010
• Description: 4Kbit / 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: ST Microelectronics

M95040, M95020, M95010
Data Protection and Protocol Control
To help protect the device from data corruption in
noisy or poorly controlled environments, a number
of safety features have been built in to the device.
The main security measures can be summarized
as follows:
– The WEL bit is reset at power-up.
– Chip Select (S) must rise after the eighth clock
– Accesses to the memory array are ignored dur-
– Invalid Chip Select (S) and Hold (HOLD) transi-
Table 3. Write-Protected Block Size
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count (or multiple thereof) in order to start a non-
volatile Write cycle (in the memory array or in
the Status Register).
ing the non-volatile programming cycle, and the
programming cycle continues unaffected.
tions are ignored.
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
Protected Block
Whole memory
Upper quarter
Upper half
none
180h - 1FFh
100h - 1FFh
000h - 1FFh
M95040
none
For any instruction to be accepted and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches the last bit of
the instruction, and before the next rising edge of
Serial Clock (C).
For this, “the last bit of the instruction” can be the
eighth bit of the instruction code, or the eighth bit
of a data byte, depending on the instruction (ex-
cept in the case of RDSR and READ instructions).
Moreover, the "next rising edge of CLOCK" might
(or might not) be the next bus transaction for some
other device on the bus.
When a Write cycle is in progress, the device pro-
tects it against external interruption by ignoring
any subsequent READ, WRITE or WRSR instruc-
tion until the present cycle is complete.
Array Addresses Protected
C0h - FFh
80h - FFh
00h - FFh
M95020
none
060h - 7Fh
040h - 7Fh
000h - 7Fh
M95010
none