M95010 ST Microelectronics, M95010 Datasheet

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... Status Register BYTE and PAGE WRITE ( Bytes) Self-Timed Programming Cycle Adjustable Size Read-Only EEPROM Area Enhanced ESD Protection More than 1,000,000 Erase/Write Cycles More than 40 Year Data Retention July 2003 M95020, M95010 With High Speed Clock Figure 1. Packages 8 1 PDIP8 (BN ...

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... SUMMARY DESCRIPTION The M95040 Kbit (512 x 8) electrically eras- able programmable memory (EEPROM), access high speed SPI-compatible bus. The other members of the family (M95020, M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible ...

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... This input signal is used to control whether the memory is write protected. When W is held Low, writes to the memory are disabled, but other oper- ations remain enabled. No action on this signal the Write Enable Latch (WEL) bit, can interrupt a Write cycle that has already started. M95040, M95020, M95010 3/33 ...

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... M95040, M95020, M95010 CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low ...

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... Figure 5. SPI Modes Supported CPOL CPHA MSB Q M95040, M95020, M95010 MSB AI01438B 5/33 ...

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... M95040, M95020, M95010 OPERATING FEATURES Power-up When the power supply is turned on, V from During this time, the Chip Select (S) must be al- lowed to follow the V voltage. It must not be al- CC lowed to float, but should be connected suitable pull-up resistor built in safety feature, Chip Select (S) is edge sensitive as well as level sensitive ...

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... When reset WRITE or WRSR instructions are accepted by the device. BP1, BP0 bits. The Block Protect bits are non- volatile read-write bits. These bits define the area M95040, M95020, M95010 of memory that is protected against the execution of Write cycles, as summarized in Table 3. Table 2. Status Register Format ...

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... M95040, M95020, M95010 Data Protection and Protocol Control To help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. The main security measures can be summarized as follows: – The WEL bit is reset at power-up. ...

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... MEMORY ORGANIZATION The memory is organized as shown in Figure 7. Figure 7. Block Diagram HOLD W Control Logic Address Register and Counter High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder M95040, M95020, M95010 Status Register Size of the Read only EEPROM area AI01272C 9/33 ...

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... M95040, M95020, M95010 INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table invalid instruction is sent (one not contained in Table 4), the device automatically deselects it- self. Figure 8. Write Enable (WREN) Sequence Write Enable (WREN) The Write Enable Latch (WEL) bit must be set pri each WRITE and WRSR instruction ...

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... Chip Select (S) be- ing driven High. The Write Enable Latch (WEL) bit, in fact, be- comes reset by any of the following events: – Power-up – WRDI instruction execution – WRSR instruction completion – WRITE instruction completion – Write Protect (W) line being held Low. M95040, M95020, M95010 11/33 ...

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... M95040, M95020, M95010 Figure 10. Read Status Register (RDSR) Sequence Instruction D High Impedance Q Read Status Register (RDSR) One of the major uses of this instruction is to allow the MCU to poll the state of the Write In Progress (WIP) bit. This is needed because the device will not accept further WRITE or WRSR instructions when the previous Write cycle is not yet finished ...

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... Write Cycle is already in progress – if the device has not been deselected, by Chip Select (S) being driven High, after the eighth bit, b0, of the data byte has been latched in – if Write Protect (W) is Low. M95040, M95020, M95010 Status Register ...

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... M95040, M95020, M95010 Figure 12. Read from Memory Array (READ) Sequence High Impedance Q Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care. Read from Memory Array (READ) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven Low ...

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... WC ing edge of Serial Clock (C) occurs anywhere on the bus) – if Write Protect (W) is Low or if the addressed page is in the region protected by the Block Pro- tect (BP1 and BP0) bits. M95040, M95020, M95010 Data Byte ...

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... M95040, M95020, M95010 Figure 14. Page Write (WRITE) Sequence Data Byte Note: Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care. 16/ ...

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... Chip Select (S) before any instruc- tions can be started). – not in the Hold Condition – the Write Enable Latch (WEL) is reset to 0 M95040, M95020, M95010 – Write In Progress (WIP) is reset to 0 the BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits) ...

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... M95040, M95020, M95010 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 6 ...

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... Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. Parameter Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC M95040, M95020, M95010 Min. Max. 4.5 5.5 –40 85 –40 125 Min. Max. 2.5 5.5 – ...

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... M95040, M95020, M95010 Table 11. Capacitance Symbol Parameter C Output Capacitance (Q) OUT C Input Capacitance (D) IN Input Capacitance (other pins) Note: Sampled only, not 100% tested Table 12. DC Characteristics (M950x0, temperature range 6) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current ...

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... C = 0.1 V /0. MHz 1 open 1 0. –0 M95040, M95020, M95010 Min. Max. Unit ± 2 µA ± 2 µ µA – 0 0 Min. Max. Unit ± ...

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... M95040, M95020, M95010 Table 17. AC Characteristics (M950x0, temperature range 6) Symbol Alt Clock Frequency C SCK Active Setup Time SLCH CSS1 Not Active Setup Time SHCH CSS2 Deselect Time SHSL Active Hold Time CHSH CSH t S Not Active Hold Time ...

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... HOLD Low to Output High HLQZ t t Write Time W WC Note Value guaranteed by characterization, not 100% tested in production. Test conditions specified in Table 10 and Table 7 Parameter M95040, M95020, M95010 Min. Max. Unit D.C. 2 MHz 100 ns 100 ns 200 ns 100 ns 200 ns 200 ns ...

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... M95040, M95020, M95010 Table 19. AC Characteristics (M950x0-W, temperature ranges 6 and 3) Symbol Alt Clock Frequency C SCK Active Setup Time SLCH CSS1 Not Active Setup Time SHCH CSS2 Deselect Time SHSL Active Hold Time CHSH CSH t S Not Active Hold Time ...

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... HOLD Low to Output High HLQZ t t Write Time W WC Note Value guaranteed by characterization, not 100% tested in production. Test conditions specified in Table 10 and Table 9 Parameter M95040, M95020, M95010 Min. Max. Unit D.C. 1 MHz 400 ns 400 ns 300 ns 400 ns 400 ns 400 ns ...

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... M95040, M95020, M95010 Figure 16. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Figure 17. Hold Timing HOLD 26/33 tSLCH tCHDX tCLCH MSB IN tHLCH tCHHL tCHHH tHLQZ tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tHHCH tHHQX AI02032 ...

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... Figure 18. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV M95040, M95020, M95010 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449D 27/33 ...

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... M95040, M95020, M95010 PACKAGE MECHANICAL PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Notes: 1. Drawing is not to scale. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data Symb. Typ 3.30 b 0.46 b2 1.52 c 0.25 D 9.27 E 7.87 E1 6.35 e 2. 3.30 28/ ...

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... Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 5.80 6.20 0.25 0.50 0.40 0.90 0° 8° 8 0.10 M95040, M95020, M95010 h x 45˚ inches Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 0.050 – 0.228 0.010 0.016 0° 8 Max. 0.069 0.010 0.020 0.010 0.197 0.157 – 0.244 0.020 0.035 8° ...

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... M95040, M95020, M95010 TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline A CP Notes: 1. Drawing is not to scale. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data Symbol Typ 1.000 3.000 e 0.650 E 6.400 E1 4.400 L 0.600 L1 1.000 30/ ...

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... All devices use a positive clock strobe: Serial Data In (D) is strobed on the rising edge of Serial Clock (C) and Serial Data Out (Q) is synchronized from the falling edge of Serial Clock (C). For a list of available options (speed, package, etc.) or for further information on any aspect of this M95040, M95020, M95010 M95040 – device, please contact your nearest ST Sales Of- fice ...

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... M95040, M95020, M95010 REVISION HISTORY Table 22. Document Revision History Date Rev. 10-May-2000 2.2 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & Tab 9. 16-Mar-2001 2.3 Wording changes, according to the standard glossary ...

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