LP2975AIMM-12 National Semiconductor, LP2975AIMM-12 Datasheet - Page 14

• Manufacturer Part Number: LP2975AIMM-12
• Description: MOSFET LDO Driver/Controller
• Manufacturer: National Semiconductor

www.national.com
Application Hints
As can be seen in the graph, values of C
500 pF–2500 pF range produce values for f
40 kHz and 700 kHz. To determine what effect f
on stability, the bandwidth of the regulator loop must be cal-
culated (see next section CROSSOVER FREQUENCY AND
PHASE MARGIN ).
Crossover Frequency and Phase Margin
The term f
the regulator loop (which is the frequency where the gain
curve crosses the 0 dB axis). The importance of this fre-
quency is that it is the point where the loop gain goes below
unity, which marks the usable bandwidth of the regulator
loop.
It is the phase margin (or lack of it) at f
whether the regulator is stable. Phase margin is defined as
the total phase shift subtracted from 180˚. In general, a
stable loop requires at least 20˚-30˚ of phase margin at f
f
have been previously defined):
This equation assumes that no C
If the frequency of the Gate capacitance pole f
calculated (previous section), the amount of added phase
shift may now be determined. As shown in the graph below
(see graph PHASE SHIFT DUE TO f
added phase shift increases as f
The amount of phase shift due to f
oscillation takes place depends on how much added phase
shift is present as a result of the C
section OUTPUT CAPACITOR).
Because of this, there is no exact number for f
be given as a fixed limit for stable operation. However, as a
general guideline, it is recommended that f
If this is not found to be true after inital calculations, the ratio
of f
a different FET) or using a larger value of C
Along with these two methods, another technique for improv-
ing loop stability is the use of a feed-forward capacitor (see
c
can be approximated by the following equation (all terms
pg
/f
c
can be increased by either reducing C
c
will be used to define the crossover frequency of
Phase Shift Due to f
(Continued)
pg
F
is used and f
pg
approaches f
OUT
that can occur before
pg
pg
pole (see previous
DS100034-23
c
), the amount of
DS100034-22
pg
that determines
OUT
EFF
pg
pg
3 f
pg
.
pg
EFF
pg
c
/f
.
c
(selecting
/f
has been
c
will have
between
.
c
that can
in the
>
1.
c
.
14
next section FEED-FORWARD COMPENSATION). This can
improve phase margin by cancelling some of the excess
phase shift.
Feed-Forward Compensation
Phase shift in the loop gain of the regulator results from f
(the pole from the output capacitor and load resistance), f
(the pole from the FET gate capacitance), as well as the IC’s
internal controller pole (see typical curve). If the total phase
shift becomes excessive, instability can result.
The total phase shift can be reduced using feed-forward
compensation, which places a zero in the loop to reduce the
effects of the poles.
The feed-forward capacitor C
it is selected to set the zero at the correct frequency. It is im-
portant to point out that the feed-forward capacitor produces
both a zero and a pole . The frequency where the zero occurs
will be defined as f
defined as f
are:
In general, the feed-forward capacitor gives the greatest im-
provement in phase margin (provides the maximum reduc-
tion in phase shift) when the zero occurs at a frequency
where the loop gain is
The pole must occur at a higher frequency (the higher the
better) where most of the phase shift added by the new pole
occurs beyond the crossover frequency. For this reason, the
pole-zero pair created by C
proving loop stability as they get farther apart in frequency.
In reviewing the equations for f
they get closer together in frequency as V
For this reason, the use of C
output voltages, declining as V
(where C
In selecting a value of feed-forward capacitor, the crossover
frequency f
quency of the zero (f
range:
The equation to determine the value of the feed-forward ca-
pacitor in fixed-voltage applications is:
In adjustable applications (using an external resistive di-
vider) the capacitor is found using:
SUMMARY OF STABILITY INFORMATION
This section will present an explanation of theory and termi-
nology used to analyze loop stability, along with specific in-
formation related to stabilizing LP2975 applications.
BODE PLOTS AND PHASE SHIFT
Loop gain information is most often presented in the form of
a Bode Plot, which plots Gain (in dB) versus Frequency (in
Hertz).
A Bode Plot also conveys phase shift information, which can
be derived from the locations of the poles and zeroes.
POLE: A pole causes the slope of the gain curve to de-
crease by an additional −20 dB/decade, and it also causes
phase lag (defined as negative phase shift) to occur.
A single pole will cause a maximum −90˚ of phase lag (see
graph EFFECTS OF A SINGLE POLE ). It should be noted
F
f
C
f
zf
pf
has no effect at all).
c
F
pf
= 6.6 x 10
= 6.6 x 10
must first be calculated. In general, the fre-
= 6.6 x 10
. The equations to calculate the frequencies
C
zf
C
zf
0.2 f
, and the frequency of the pole will be
) set by this capacitor should be in the
= 1/(2
>
-6
-6
-6
1 (before the crossover frequency).
/ [C
c
/ [C
/ [f
F
F
zf
F
F
f
F
gives greatest benefit at higher
zf
become more effective at im-
can accomplish this, provided
x (V
x (V
x (1 − 1.24/V
zf
x R1 x f
and f
1.0 f
OUT
OUT
OUT
c
/1.24 − 1) ]
pf
/1.24 − 1) ]
zf
, it can be seen that
approaches 1.24V
)
OUT
OUT
)]
decreases.
pg
p