Z89139 Zilog., Z89139 Datasheet - Page 50

• Manufacturer Part Number: Z89139
• Description: Voice Processing Controllers
• Manufacturer: Zilog.

Z89138/Z89139
Voice Processing Controllers
DSP IRQ0. This bit defines the source of the DSP IRQ0 in-
terrupt.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A Sampling
Rate (Table 18).
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and can be used
to output data by writing to bit 6.
DSP1. DSP1 is a general-purpose output pin connected to
Bit 7. This bit has no special significance and can be used
to output data by writing to bit 7.
DSP TIMERS
Timer2 is a free running counter that divides the XTAL fre-
quency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the An-
alog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
50
D/A_Sampling Rate
Bit 8
0
1
Table 18. D/A Data Accuracy
20.48 MHz
16 kHz
10 kHz
Sampling Rate
20.48 MHz
29.49 MHz
OSC
USC
29.49 MHz
Figure 37. Timer2 and Timer3
8.04 kHz
9.6 kHz
P R E L I M I N A R Y
8.04, 9.6 kHz
16, 9.6 kHz
8, 16 kHz
16, 10 kHz
Timer2
Timer2
Timer3
Timer3
Enable A/D. Writing a 0 to this location disables the A/D
converter, a 1 will enable it. A hardware reset forces this
bit to 0.
Conversion Done. This Read-Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D da-
ta), the Conversion Done flag is cleared.
Start A/D Conversion. Writing a 1 to this location immedi-
ately starts one conversion cycle. If this bit is reset to 0 the
input data is converted upon successive Timer2 time-outs.
A hardware reset forces this bit to 1.
A/D_Sampling Rate. This field defines the sampling rate
of the A/D. It changes the period of Timer2 interrupt (Table
19).
Analogous to Timer2, Timer3 generates the different sam-
pling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 37).
A/D_Sampling Rate
Bit 0
1
0
Table 19. A/D Sampling Rate
D/A
A/D
D/A
A/D
20.48 MHz
16 kHz
8 kHz
Sampling Rate
DS97TAD0201
29.49 MHz
9.6 kHz
16 kHz
Zilog