Z89139 Zilog., Z89139 Datasheet - Page 45

• Manufacturer Part Number: Z89139
• Description: Voice Processing Controllers
• Manufacturer: Zilog.

Zilog
DSP Interrupts
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 32). These sources have different pri-
ority levels (Figure 33). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
DS97TAD0201
interrupt DSP via DSP INT2.
After serving IRQ3,
set D0 to clear the
interrupt request.
A/D INT
D/A INT
FB DSP
Z8_INT
On the Z8, set D1 to
IPR2
IPR1
IPR0
Z8 Side
DSP CON
IRQ3 of the Z8
Interrupt Priority Logic
FeedBack Z8_INT MPX
DSP Execution
Figure 34. Interprocessor Interrupts Structure
Figure 33. DSP Interrupt Priority Structure
INT0
INT1
INT2
Figure 32. DSP Interrupts
P R E L I M I N A R Y
Interrupt Request Logic
INT2
9
and INT0, respectively (Figure 34). The DSP does not al-
low interrupt nesting (interrupting service routines that are
currently being executed). When two interrupt requests oc-
cur simultaneously the DSP starts servicing the interrupt
with the highest priority level.
1
INT0
0
INT1
INT2
INT1
INT0
CLEAR_INT0
CLEAR_INT1
CLEAR_INT2
ENABLE_INT
4
DSP INT2
INT2
Interrupt Mask Logic
interrupt Z8 via Z8 IRQ3.
The DSP sets D9 to
After serving INT2,
set D4 to clear the
interrupt request.
Voice Processing Controllers
DSP Side
INT2
INT1
INT0
(EXT4)
ICR
Z89138/Z89139
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