Z89139 Zilog., Z89139 Datasheet - Page 40

• Manufacturer Part Number: Z89139
• Description: Voice Processing Controllers
• Manufacturer: Zilog.

Z8 FUNCTIONAL DESCRIPTION (Continued)
Z89138/Z89139
Voice Processing Controllers
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subse-
quent executions of the WDT instruction. The WDT circuit
Half-Second Timer Status Register (HSEC). The half-
second timer status register (Figure 29) is a free-running
timer clocked by the external 32.768 kHz crystal. In normal
operation mode, every half-second, the timer will time-out
and set bit 0 (D0) of the HSEC register to 1. The user can
reset this bit for real timing. In Stop mode, this timer can be
used as a Stop-Mode Recovery source. Every half-sec-
ond, the timer will recover the Stop mode and bit 0 of the
HSEC register will be set to 1. Therefore, in STOP Mode,
the user can keep real time.
40
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after RESET
Figure 28. Watch-Dog Timer Mode Register
P R E L I M I N A R Y
WDT TAP
00
01*
10
11
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
W No effect
R Always "1"
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 28). The WDTMR
register is accessible only within 64 Z8 clock cycles after
POR.
HSEC (F) 0E
D7 D6 D5 D4 D3 D2 D1 D0
Figure 29. Half-Second Timer Status Register
INT RC OSC
100 ms
15 ms
25 ms
5 ms
EXTERNAL CLOCK
4096 Tpc
1024 Tpc
512 Tpc
256 Tpc
R 1 Half second time-out
W 1 No effect
Reserved R "0"
0 No time-out
0 RESET the half second timer bit
W No effect
DS97TAD0201
Zilog