HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 241
![no-image](/images/no-image-200.jpg)
HD6433044
Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6433044.pdf
(867 pages)
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Figure 8-15 shows an auto-requested burst-mode transfer. This example shows a transfer of three
words from a 16-bit two-state access area to another 16-bit two-state access area.
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode
and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the
pin is next sampled at the end of one block transfer.
ø
Address
bus
RD
HWR
LWR
,
CPU cycle
T
1
T
2
T
d
Figure 8-15 Burst DMA Bus Timing
T
1
Source
address
T
2
T
Destination
address
1
T
2
227
T
DMAC cycle
1
T
2
T
1
T
2
T
1
T
2
T
1
T
2
T
CPU cyc
1
T
2
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