HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 168
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HD6433044
Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6433044.pdf
(867 pages)
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Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
PSRAME = 1 or DRAME = 1.
Bit 6
CMIE
0
1
Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for
input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at
periodic intervals determined by compare match between RTCNT and RTCOR. When used as an
interval timer, the refresh controller generates CMI interrupts at periodic intervals determined by
compare match. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1.
Bit 5
CKS2
0
1
Bits 2 to 0—Reserved: Read-only bits, always read as 1.
Description
The CMI interrupt requested by CMF is disabled
The CMI interrupt requested by CMF is enabled
Bit 4
CKS1
0
1
0
1
Bit 3
CKS0
0
1
0
1
0
1
0
1
Description
Clock input is disabled
ø/2 clock source
ø/8 clock source
ø/32 clock source
ø/128 clock source
ø/512 clock source
ø/2048 clock source
ø/4096 clock source
154
(Initial value)
(Initial value)
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